[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor branch instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40886 )
Change subject: arch-power: Refactor branch instructions
..
arch-power: Refactor branch instructions
This changes the base classes for branch instructions and
switches to two high-level classes for unconditional and
conditional branches. The conditional branches are further
classified based on whether they use an immediate field or
a register for determining the target address.
Decoding has also been consolidated using formats that can
generate code after determining if an instruction branches
to an absolute address or a PC-relative address, or if it
implicitly sets the return address by looking at the AA and
LK bits.
Change-Id: I5fa7db7b6693586b4ea3c71e5cad8a60753de29c
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40886
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/power/insts/branch.cc
M src/arch/power/insts/branch.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/branch.isa
M src/arch/power/isa/formats/util.isa
M src/arch/power/types.hh
6 files changed, 224 insertions(+), 330 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index 84834f1..1077f33 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -49,21 +49,30 @@
return *cachedDisassembly;
}
+
PowerISA::PCState
-BranchPCRel::branchTarget(const PowerISA::PCState &pc) const
+BranchOp::branchTarget(const PowerISA::PCState &pc) const
{
-return (uint32_t)(pc.pc() + disp);
+if (aa)
+return li;
+else
+return pc.pc() + li;
}
+
std::string
-BranchPCRel::generateDisassembly(
+BranchOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream ss;
+Addr target;
ccprintf(ss, "%-10s ", mnemonic);
-Addr target = pc + disp;
+if (aa)
+target = li;
+else
+target = pc + li;
Loader::SymbolTable::const_iterator it;
if (symtab && (it = symtab->find(target)) != symtab->end())
@@ -74,46 +83,34 @@
return ss.str();
}
+
PowerISA::PCState
-BranchNonPCRel::branchTarget(const PowerISA::PCState &pc) const
+BranchDispCondOp::branchTarget(const PowerISA::PCState &pc) const
{
-return targetAddr;
+if (aa) {
+return bd;
+} else {
+return pc.pc() + bd;
+}
}
+
std::string
-BranchNonPCRel::generateDisassembly(
+BranchDispCondOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream ss;
+Addr target;
ccprintf(ss, "%-10s ", mnemonic);
-Loader::SymbolTable::const_iterator it;
-if (symtab && (it = symtab->find(targetAddr)) != symtab->end())
-ss << it->name;
+// Print BI and BO fields
+ss << bi << ", " << bo << ", ";
+
+if (aa)
+target = bd;
else
-ccprintf(ss, "%#x", targetAddr);
-
-return ss.str();
-}
-
-PowerISA::PCState
-BranchPCRelCond::branchTarget(const PowerISA::PCState &pc) const
-{
-return (uint32_t)(pc.pc() + disp);
-}
-
-std::string
-BranchPCRelCond::generateDisassembly(
-Addr pc, const Loader::SymbolTable *symtab) const
-{
-std::stringstream ss;
-
-ccprintf(ss, "%-10s ", mnemonic);
-
-ss << bo << ", " << bi << ", ";
-
-Addr target = pc + disp;
+target = pc + bd;
Loader::SymbolTable::const_iterator it;
if (symtab && (it = symtab->find(target)) != symtab->end())
@@ -124,47 +121,25 @@
return ss.str();
}
+
PowerISA::PCState
-BranchNonPCRelCond::branchTarget(const PowerISA::PCState &pc) const
+BranchRegCondOp::branchTarget(ThreadContext *tc) const
{
-return targetAddr;
+Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index());
+return addr & -4ULL;
}
+
std::string
-BranchNonPCRelCond::generateDisassembly(
+BranchRegCondOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
-ss << bo << ", " << bi << ", ";
-
-Loader::SymbolTable::const_iterator it;
-if (symtab && (it = symtab->find(targetAddr)) != symtab->end())
-ss << it->name;
-else
-ccprintf(ss, "%#x", targetAddr);
-
-return ss.str();
-}
-
-PowerISA::PCState
-BranchRegCond::branchTarget(ThreadContext *tc) const
-{
-uint32_t regVal = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index());
-return regVal & 0xfffc;
-}
-
-std::string
-BranchRegCond::generateDisassembly(
-Addr pc, const Loader::SymbolTable *symtab) const
-{
-std::stringstream ss;
-
-ccprintf(ss, "%-10s ", mnemonic);
-
-ss << bo << ", " << bi << ", ";
+// Print
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor branch instructions
Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40886 )
Change subject: arch-power: Refactor branch instructions
..
arch-power: Refactor branch instructions
This changes the base classes for branch instructions and
switches to two high-level classes for unconditional and
conditional branches. The conditional branches are further
classified based on whether they use an immediate field or
a register for determining the target address.
Decoding has also been consolidated using formats that can
generate code after determining if an instruction branches
to an absolute address or a PC-relative address, or if it
implicitly sets the return address by looking at the AA and
LK bits.
Change-Id: I5fa7db7b6693586b4ea3c71e5cad8a60753de29c
Signed-off-by: Sandipan Das
---
M src/arch/power/insts/branch.cc
M src/arch/power/insts/branch.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/branch.isa
M src/arch/power/isa/formats/util.isa
M src/arch/power/types.hh
6 files changed, 268 insertions(+), 331 deletions(-)
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index 72e4412..26a3c74 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -52,21 +52,32 @@
return *cachedDisassembly;
}
+
PowerISA::PCState
-BranchPCRel::branchTarget(const PowerISA::PCState &pc) const
+BranchOp::branchTarget(const PowerISA::PCState &pc) const
{
-return (uint32_t)(pc.pc() + disp);
+if (aaSet) {
+return disp;
+} else {
+return pc.pc() + disp;
+}
}
+
std::string
-BranchPCRel::generateDisassembly(
+BranchOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream ss;
+Addr target;
ccprintf(ss, "%-10s ", mnemonic);
-Addr target = pc + disp;
+if (aaSet) {
+target = disp;
+} else {
+target = pc + disp;
+}
Loader::SymbolTable::const_iterator it;
if (symtab && (it = symtab->find(target)) != symtab->end())
@@ -77,46 +88,35 @@
return ss.str();
}
+
PowerISA::PCState
-BranchNonPCRel::branchTarget(const PowerISA::PCState &pc) const
+BranchDispCondOp::branchTarget(const PowerISA::PCState &pc) const
{
-return targetAddr;
+if (aaSet) {
+return disp;
+} else {
+return pc.pc() + disp;
+}
}
+
std::string
-BranchNonPCRel::generateDisassembly(
+BranchDispCondOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream ss;
+Addr target;
ccprintf(ss, "%-10s ", mnemonic);
-Loader::SymbolTable::const_iterator it;
-if (symtab && (it = symtab->find(targetAddr)) != symtab->end())
-ss << it->name;
-else
-ccprintf(ss, "%#x", targetAddr);
+// Print BI and BO fields
+ss << crBit << ", " << opts << ", ";
-return ss.str();
-}
-
-PowerISA::PCState
-BranchPCRelCond::branchTarget(const PowerISA::PCState &pc) const
-{
-return (uint32_t)(pc.pc() + disp);
-}
-
-std::string
-BranchPCRelCond::generateDisassembly(
-Addr pc, const Loader::SymbolTable *symtab) const
-{
-std::stringstream ss;
-
-ccprintf(ss, "%-10s ", mnemonic);
-
-ss << bo << ", " << bi << ", ";
-
-Addr target = pc + disp;
+if (aaSet) {
+target = disp;
+} else {
+target = pc + disp;
+}
Loader::SymbolTable::const_iterator it;
if (symtab && (it = symtab->find(target)) != symtab->end())
@@ -127,47 +127,25 @@
return ss.str();
}
+
PowerISA::PCState
-BranchNonPCRelCond::branchTarget(const PowerISA::PCState &pc) const
+BranchRegCondOp::branchTarget(ThreadContext *tc) const
{
-return targetAddr;
+Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index());
+return addr & -4ULL;
}
+
std::string
-BranchNonPCRelCond::generateDisassembly(
+BranchRegCondOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
-ss << bo << ", " << bi << ", ";
-
-Loader::SymbolTable::const_iterator it;
-if (symtab && (it = symtab->find(targetAddr)) != symtab->end())
-ss << it->name;
-else
-ccprintf(ss, "%#x", targetAddr);
-
-return ss.str();
-}
-
-PowerISA::PCState
-BranchRegCond::branchTarget(ThreadContext *tc) const
-{
-uint32_t regVal = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index());
-return regVal & 0xfffc;
-}
-
-std::string
-BranchRegCond::generateDisassembly(
-Addr pc, const Loader::SymbolTable *symtab) const
-{
-std::stringstream ss;
-
-ccprintf(ss, "%-10s ", mnemonic);
-
-ss << bo << ", " << bi << ", ";
+// Print the BI and BO fields
+ss << crBit << ", " << opts;
return ss.str();
}
diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh
index 435b4fd..8c311a2 100
