Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57019 )
Change subject: arch-x86: Add ldio and stio microops for IO port access.
......................................................................
arch-x86: Add ldio and stio microops for IO port access.
Instead of using an "internal" segment to access IO ports, the only
remaining use of the internal segment, use specialized microops instead.
From the perspective of simulation this should be basically functionally
equivalent, but it simplifies the microcode, simplifies the
communication with the TLB, simplifies the TLB implementation, frees up
some bits for x86 specific memory request flags, and makes the special
"internal" segment available for other uses. It was never very clear
what the "internal" segment was actually supposed to be for, I had just
made something up that seemed plausible. If another plausible use comes
up, then it could be reused for that.
Change-Id: Ib1b7c13c58a9a70c1290bbee3229bcb532a45afe
---
M src/arch/amdgpu/common/tlb.cc
M src/arch/amdgpu/common/tlb.hh
M src/arch/x86/insts/microldstop.hh
M src/arch/x86/insts/microop_args.hh
M src/arch/x86/isa/microops/ldstop.isa
M src/arch/x86/isa/operands.isa
M src/arch/x86/ldstflags.hh
M src/arch/x86/microcode/general_purpose/input_output/general_io.ucode
M src/arch/x86/microcode/general_purpose/input_output/string_io.ucode
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
M src/arch/x86/ucasmlib/arch/x86/microops/ldstop.py
M src/arch/x86/x86_traits.hh
13 files changed, 303 insertions(+), 101 deletions(-)
diff --git a/src/arch/amdgpu/common/tlb.cc b/src/arch/amdgpu/common/tlb.cc
index 6b98363..7afe176 100644
--- a/src/arch/amdgpu/common/tlb.cc
+++ b/src/arch/amdgpu/common/tlb.cc
@@ -274,32 +274,6 @@
}
}
-
-
- Fault
- GpuTLB::translateInt(bool read, const RequestPtr &req, ThreadContext
*tc)
- {
- DPRINTF(GPUTLB, "Addresses references internal memory.\n");
- Addr vaddr = req->getVaddr();
- Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
-
- if (prefix == IntAddrPrefixIO) {
- // TODO If CPL > IOPL or in virtual mode, check the I/O
permission
- // bitmap in the TSS.
-
- Addr IOPort = vaddr & ~IntAddrPrefixMask;
- // Make sure the address fits in the expected 16 bit IO address
- // space.
- assert(!(IOPort & ~0xFFFF));
- req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
- req->setPaddr(PhysAddrPrefixIO | IOPort);
- return NoFault;
- } else {
- panic("Access to unrecognized internal address space %#x.\n",
- prefix);
- }
- }
-
/**
* TLB_lookup will only perform a TLB lookup returning true on a TLB
hit
* and false on a TLB miss.
@@ -361,21 +335,28 @@
Translation *translation, Mode mode,
bool &delayedResponse, bool timing, int &latency)
{
- uint32_t flags = req->getFlags();
- int seg = flags & SegmentFlagMask;
- bool storeCheck = flags & Request::READ_MODIFY_WRITE;
-
- // If this is true, we're dealing with a request
- // to a non-memory address space.
- if (seg == SEGMENT_REG_MS) {
- return translateInt(mode == Mode::Read, req, tc);
- }
+ const Request::Flags flags = req->getFlags();
delayedResponse = false;
- Addr vaddr = req->getVaddr();
+
+ const Addr vaddr = req->getVaddr();
+
+ // If this is true, we're dealing with a request to a non-memory
+ // address space.
+ if (flags & IOFlagBit) {
+ DPRINTF(GPUTLB, "Translating IO port %#x.\n", vaddr);
+
+ // Make sure the IO port is within the valid range.
+ assert((vaddr & ~mask(16)) == 0);
+
+ req->setPaddr(PhysAddrPrefixIO | vaddr);
+ return NoFault;
+ }
+
DPRINTF(GPUTLB, "Translating vaddr %#x.\n", vaddr);
- HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+ const bool storeCheck = flags & Request::READ_MODIFY_WRITE;
+ const HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
// If protected mode has been enabled...
if (m5Reg.prot) {
diff --git a/src/arch/amdgpu/common/tlb.hh b/src/arch/amdgpu/common/tlb.hh
index dec0d61..4c65a85 100644
--- a/src/arch/amdgpu/common/tlb.hh
+++ b/src/arch/amdgpu/common/tlb.hh
@@ -158,9 +158,6 @@
*/
std::vector<EntryList> entryList;
- Fault translateInt(bool read, const RequestPtr &req,
- ThreadContext *tc);
-
Fault translate(const RequestPtr &req, ThreadContext *tc,
Translation *translation, Mode mode, bool &delayedResponse,
bool timing, int &latency);
diff --git a/src/arch/x86/insts/microldstop.hh
b/src/arch/x86/insts/microldstop.hh
index 90b8058..980deb7 100644
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -55,6 +55,37 @@
{
/**
+ * Base class for IO port ops
+ */
+class IoOp : public X86MicroopBase
+{
+ protected:
+ IoOp(ExtMachInst mach_inst, const char *mnem, const char *inst_mnem,
+ uint64_t set_flags, OpClass op_class, uint8_t data_size) :
+ X86MicroopBase(mach_inst, mnem, inst_mnem, set_flags, op_class),
+ dataSize(data_size)
+ {}
+
+ public:
+ const uint8_t dataSize;
+};
+
+/**
+ * Base class for the actual IO load or store
+ */
+class LdStIoOp : public InstOperands<IoOp, IntDataOp, PortOp>
+{
+ protected:
+ LdStIoOp(ExtMachInst mach_inst, const char *mnem, const char
*inst_mnem,
+ uint64_t set_flags, GpRegIndex _data, GpRegIndex io_port,
+ uint8_t data_size, OpClass op_class) :
+ InstOperands<IoOp, IntDataOp, PortOp>(
+ mach_inst, mnem, inst_mnem, set_flags, op_class,
+ { _data, io_port }, data_size)
+ {}
+};
+
+/**
* Base class for memory ops
*/
class MemOp : public X86MicroopBase
@@ -98,7 +129,7 @@
InstOperands<MemOp, FoldedDataOp, AddrOp>(
mach_inst, mnem, inst_mnem, set_flags, op_class,
{ _data, { _scale, _index, _base, _disp, _segment } },
- data_size, address_size, mem_flags | _segment.index)
+ data_size, address_size, mem_flags)
{}
};
@@ -117,7 +148,7 @@
InstOperands<MemOp, FloatDataOp, AddrOp>(
mach_inst, mnem, inst_mnem, set_flags, op_class,
{ _data, { _scale, _index, _base, _disp, _segment } },
- data_size, address_size, mem_flags | _segment.index)
+ data_size, address_size, mem_flags)
{}
};
@@ -135,7 +166,7 @@
InstOperands<MemOp, AddrOp>(
mach_inst, mnem, inst_mnem, set_flags, op_class,
{ { _scale, _index, _base, _disp, _segment } },
- data_size, address_size, mem_flags | _segment.index)
+ data_size, address_size, mem_flags)
{}
};
@@ -157,7 +188,7 @@
InstOperands<MemOp, FoldedDataLowOp, FoldedDataHiOp, AddrOp>(
mach_inst, mnem, inst_mnem, set_flags, op_class,
{ data_low, data_hi, { _scale, _index, _base, _disp, _segment
} },
- data_size, address_size, mem_flags | _segment.index)
+ data_size, address_size, mem_flags)
{}
};
diff --git a/src/arch/x86/insts/microop_args.hh
b/src/arch/x86/insts/microop_args.hh
index 7769764..1c09013 100644
--- a/src/arch/x86/insts/microop_args.hh
+++ b/src/arch/x86/insts/microop_args.hh
@@ -276,6 +276,7 @@
using FloatDataOp = FloatOp<DataOp>;
using FoldedDataHiOp = FoldedOp<DataHiOp>;
using FoldedDataLowOp = FoldedOp<DataLowOp>;
+using IntDataOp = IntOp<DataOp>;
struct Imm8Op
{
@@ -377,6 +378,25 @@
}
};
+struct PortOp
+{
+ using ArgType = GpRegIndex;
+ const RegIndex ioPort;
+ const size_t size;
+ RegIndex opIndex() const { return ioPort; }
+
+ template <class InstType>
+ PortOp(InstType *inst, const ArgType &io_port) :
+ ioPort(io_port.index), size(2)
+ {}
+
+ void
+ print(std::ostream &os) const
+ {
+ X86StaticInst::printReg(os, RegId(IntRegClass, ioPort), size);
+ }
+};
+
template <typename Base, typename ...Operands>
class InstOperands : public Base, public Operands...
{
diff --git a/src/arch/x86/isa/microops/ldstop.isa
b/src/arch/x86/isa/microops/ldstop.isa
index 2806f1e..6631d70 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -251,6 +251,140 @@
}
}};
+// IO load templates
+
+def template LdioExecute {{
+ Fault
+ %(class_name)s::execute(ExecContext *xc,
+ Trace::InstRecord *traceData) const
+ {
+ %(op_decl)s;
+ %(op_rd)s;
+ %(addr_code)s;
+
+ Fault fault = readMemAtomic(xc, traceData, io_port,
Mem, %(data_size)s,
+ X86ISA::IOFlagBit | Request::PHYSICAL |
Request::UNCACHEABLE |
+ Request::STRICT_ORDER);
+ if (fault)
+ return fault;
+
+ %(code)s;
+ %(op_wb)s;
+
+ return NoFault;
+ }
+}};
+
+def template LdioInitiateAcc {{
+ Fault
+ %(class_name)s::initiateAcc(ExecContext *xc,
+ Trace::InstRecord *traceData) const
+ {
+ %(op_decl)s;
+ %(op_rd)s;
+ %(addr_code)s;
+
+ return initiateMemRead(xc, traceData, io_port, %(data_size)s,
+ X86ISA::IOFlagBit | Request::PHYSICAL |
Request::UNCACHEABLE |
+ Request::STRICT_ORDER);
+ }
+}};
+
+def template LdioCompleteAcc {{
+ Fault
+ %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
+ Trace::InstRecord *traceData) const
+ {
+ %(op_decl)s;
+ %(op_rd)s;
+
+ getMem(pkt, Mem, dataSize, traceData);
+
+ %(code)s;
+ %(op_wb)s;
+
+ return NoFault;
+ }
+}};
+
+// IO store templates
+
+def template StioExecute {{
+ Fault
+ %(class_name)s::execute(ExecContext *xc,
+ Trace::InstRecord *traceData) const
+ {
+ %(op_decl)s;
+ %(op_rd)s;
+ %(addr_code)s;
+ %(code)s;
+
+ Fault fault = writeMemAtomic(xc, traceData, Mem, %(data_size)s,
+ io_port, X86ISA::IOFlagBit | Request::PHYSICAL |
+ Request::UNCACHEABLE | Request::STRICT_ORDER, nullptr);
+ if (fault)
+ return fault;
+
+ %(op_wb)s;
+ return NoFault;
+ }
+}};
+
+def template StioInitiateAcc {{
+ Fault
+ %(class_name)s::initiateAcc(ExecContext *xc,
+ Trace::InstRecord *traceData) const
+ {
+ %(op_decl)s;
+ %(op_rd)s;
+ %(addr_code)s;
+ %(code)s;
+
+ return writeMemTiming(xc, traceData, Mem, %(data_size)s, io_port,
+ X86ISA::IOFlagBit | Request::PHYSICAL |
Request::UNCACHEABLE |
+ Request::STRICT_ORDER, nullptr);
+ }
+}};
+
+def template StioCompleteAcc {{
+ Fault
+ %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
+ Trace::InstRecord *traceData) const
+ {
+ return NoFault;
+ }
+}};
+
+def template LdStIoDeclare {{
+ class %(class_name)s : public %(base_class)s
+ {
+ private:
+ %(reg_idx_arr_decl)s;
+
+ public:
+ %(class_name)s(ExtMachInst mach_inst, const char *inst_mnem,
+ uint64_t set_flags, GpRegIndex _data, GpRegIndex io_port,
+ uint8_t data_size);
+
+ Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
override;
+ Fault completeAcc(PacketPtr, ExecContext *,
+ Trace::InstRecord *) const override;
+ };
+}};
+
+def template LdStIoConstructor {{
+ %(class_name)s::%(class_name)s(ExtMachInst mach_inst,
+ const char *inst_mnem, uint64_t set_flags,
+ GpRegIndex _data, GpRegIndex io_port, uint8_t data_size) :
+ %(base_class)s(mach_inst, "%(mnemonic)s", inst_mnem, set_flags,
+ _data, io_port, data_size, %(op_class)s)
+ {
+ %(set_reg_idx_arr)s;
+ %(constructor)s;
+ }
+}};
+
let {{
# Make these empty strings so that concatenating onto
@@ -277,7 +411,7 @@
'''
calc_check_linear = '''
// Perform segmentation checks.
- if (machInst.mode.mode != X86ISA::LongMode && segment !=
SEGMENT_REG_MS) {
+ if (machInst.mode.mode != X86ISA::LongMode) {
Fault fault = segmentationCheck(effective,
(SegmentRegIndex)segment,
SegBase, %(data_size)s, %(is_load)s, xc->tcBase());
if (fault)
@@ -302,6 +436,12 @@
linear_no_check_code = calc_effective + calc_linear + linear_debug_code
+ io_port_code = r'''
+ Addr io_port = IoPort & mask(16);
+ DPRINTF(X86, "%s : %s: The IO port is %#x.\n",
+ instMnem, mnemonic, io_port);
+ '''
+
for cls in microopClasses.loadops:
if cls.is_float:
base = 'X86ISA::LdStFpOp'
@@ -390,4 +530,24 @@
"data_size": "dataSize" })
header_output += MicroLeaDeclare.subst(iop)
exec_output += MicroLeaExecute.subst(iop)
+
+ iop = InstObjParams("ldio", "Ldio", 'X86ISA::LdStIoOp',
+ { "code": "Data = merge(Data, data, Mem, dataSize);",
+ "addr_code": io_port_code,
+ "data_size": "dataSize" })
+ header_output += LdStIoDeclare.subst(iop)
+ decoder_output += LdStIoConstructor.subst(iop)
+ exec_output += LdioExecute.subst(iop)
+ exec_output += LdioInitiateAcc.subst(iop)
+ exec_output += LdioCompleteAcc.subst(iop)
+
+ iop = InstObjParams("stio", "Stio", 'X86ISA::LdStIoOp',
+ { "code": "Mem = PData;",
+ "addr_code": io_port_code,
+ "data_size": "dataSize" })
+ header_output += LdStIoDeclare.subst(iop)
+ decoder_output += LdStIoConstructor.subst(iop)
+ exec_output += StioExecute.subst(iop)
+ exec_output += StioInitiateAcc.subst(iop)
+ exec_output += StioCompleteAcc.subst(iop)
}};
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index f07db14..c598372 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -97,6 +97,7 @@
'SrcReg2': intReg('src2', 2),
'PSrcReg2': pickedReg('src2', 2),
'SPSrcReg2': signedPickedReg('src2', 2),
+ 'IoPort': intReg('ioPort', 3),
'Index': intReg('index', 3),
'Base': intReg('base', 4),
'DestReg': intReg('dest', 5),
diff --git a/src/arch/x86/ldstflags.hh b/src/arch/x86/ldstflags.hh
index d22778f..bd40761 100644
--- a/src/arch/x86/ldstflags.hh
+++ b/src/arch/x86/ldstflags.hh
@@ -39,8 +39,6 @@
#define __ARCH_X86_LDSTFLAGS_HH__
#include "base/bitfield.hh"
-#include "base/compiler.hh"
-#include "mem/request.hh"
namespace gem5
{
@@ -51,8 +49,9 @@
namespace X86ISA
{
-constexpr Request::FlagsType SegmentFlagMask = mask(4);
-constexpr auto CPL0FlagShift = 4;
+constexpr auto IOFlagShift = 0;
+constexpr auto IOFlagBit = 1 << IOFlagShift;
+constexpr auto CPL0FlagShift = 1;
constexpr auto CPL0FlagBit = 1 << CPL0FlagShift;
} // namespace X86ISA
diff --git
a/src/arch/x86/microcode/general_purpose/input_output/general_io.ucode
b/src/arch/x86/microcode/general_purpose/input_output/general_io.ucode
index 3b74e70..58df96e 100644
--- a/src/arch/x86/microcode/general_purpose/input_output/general_io.ucode
+++ b/src/arch/x86/microcode/general_purpose/input_output/general_io.ucode
@@ -41,8 +41,7 @@
.adjust_imm trimImm(8)
limm t1, imm, dataSize=8
mfence
- ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
- nonSpec=True
+ ldio reg, t1
mfence
};
@@ -53,10 +52,8 @@
def macroop IN {
.args 'R', 'R'
- zexti t2, regm, 15, dataSize=8
mfence
- ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
- nonSpec=True
+ ldio reg, regm
mfence
};
@@ -70,8 +67,7 @@
.adjust_imm trimImm(8)
limm t1, imm, dataSize=8
mfence
- st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
- nonSpec=True
+ stio reg, t1
mfence
};
@@ -84,8 +80,7 @@
.args 'R', 'R'
zexti t2, reg, 15, dataSize=8
mfence
- st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
- nonSpec=True
+ stio regm, reg
mfence
};
diff --git
a/src/arch/x86/microcode/general_purpose/input_output/string_io.ucode
b/src/arch/x86/microcode/general_purpose/input_output/string_io.ucode
index 92d0729..40157fc 100644
--- a/src/arch/x86/microcode/general_purpose/input_output/string_io.ucode
+++ b/src/arch/x86/microcode/general_purpose/input_output/string_io.ucode
@@ -44,8 +44,7 @@
zexti t2, reg, 15, dataSize=8
mfence
- ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
- nonSpec=True
+ ldio t6, t2
st t6, es, [1, t0, rdi]
mfence
@@ -71,8 +70,7 @@
mfence
topOfLoop:
- ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
- nonSpec=True
+ ldio t6, t2
st t6, es, [1, t0, rdi]
subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
@@ -100,8 +98,7 @@
mfence
ld t6, ds, [1, t0, rsi]
- st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
- nonSpec=True
+ stio t6, t2
mfence
add rsi, rsi, t3, dataSize=asz
@@ -127,8 +124,7 @@
mfence
topOfLoop:
ld t6, ds, [1, t0, rsi]
- st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
- nonSpec=True
+ stio t6, t2
subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
add rsi, rsi, t3, dataSize=asz
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 6ef29dd..90533e9 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -173,29 +173,6 @@
}
Fault
-TLB::translateInt(bool read, RequestPtr req, ThreadContext *tc)
-{
- DPRINTF(TLB, "Addresses references internal memory.\n");
- Addr vaddr = req->getVaddr();
- Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
- if (prefix == IntAddrPrefixIO) {
- // TODO If CPL > IOPL or in virtual mode, check the I/O permission
- // bitmap in the TSS.
-
- Addr IOPort = vaddr & ~IntAddrPrefixMask;
- // Make sure the address fits in the expected 16 bit IO address
- // space.
- assert(!(IOPort & ~0xFFFF));
- req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
- req->setPaddr(PhysAddrPrefixIO | IOPort);
- return NoFault;
- } else {
- panic("Access to unrecognized internal address space %#x.\n",
- prefix);
- }
-}
-
-Fault
TLB::finalizePhysical(const RequestPtr &req,
ThreadContext *tc, BaseMMU::Mode mode) const
{
@@ -249,22 +226,28 @@
ThreadContext *tc, BaseMMU::Translation *translation,
BaseMMU::Mode mode, bool &delayedResponse, bool timing)
{
- Request::Flags flags = req->getFlags();
- int seg = flags & SegmentFlagMask;
- bool storeCheck = flags & Request::READ_MODIFY_WRITE;
+ const Request::Flags flags = req->getFlags();
delayedResponse = false;
+ const Addr vaddr = req->getVaddr();
+
// If this is true, we're dealing with a request to a non-memory
address
// space.
- if (seg == SEGMENT_REG_MS) {
- return translateInt(mode == BaseMMU::Read, req, tc);
+ if (flags & IOFlagBit) {
+ DPRINTF(TLB, "Translating IO port %#x.\n", vaddr);
+
+ // Make sure the IO port is within the valid range.
+ assert((vaddr & ~mask(16)) == 0);
+
+ req->setPaddr(PhysAddrPrefixIO | vaddr);
+ return NoFault;
}
- Addr vaddr = req->getVaddr();
DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
- HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+ const bool storeCheck = flags & Request::READ_MODIFY_WRITE;
+ const HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
// If protected mode has been enabled...
if (m5Reg.prot) {
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 68fe259..62ca8e7 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -114,8 +114,6 @@
statistics::Scalar wrMisses;
} stats;
- Fault translateInt(bool read, RequestPtr req, ThreadContext *tc);
-
Fault translate(const RequestPtr &req, ThreadContext *tc,
BaseMMU::Translation *translation, BaseMMU::Mode mode,
bool &delayedResponse, bool timing);
diff --git a/src/arch/x86/ucasmlib/arch/x86/microops/ldstop.py
b/src/arch/x86/ucasmlib/arch/x86/microops/ldstop.py
index 960fc18..4295b8f 100644
--- a/src/arch/x86/ucasmlib/arch/x86/microops/ldstop.py
+++ b/src/arch/x86/ucasmlib/arch/x86/microops/ldstop.py
@@ -116,6 +116,18 @@
{self.scale}, {self.index}, {self.base}, {self.disp},
{self.segment})'''
+class LdStIoOp(X86Microop):
+ def __init__(self, data, addr, dataSize="env.dataSize"):
+ self.data = data
+ self.addr = addr
+ self.dataSize = dataSize
+
+ def getAllocator(self, microFlags):
+ return f'''new {self.className}(machInst, macrocodeBlock,
+ {self.microFlagsText(microFlags)} |
+ (1ULL << StaticInst::IsNonSpeculative),
+ {self.data}, {self.addr}, {self.dataSize})'''
+
loadops = []
def defineMicroLoadOp(Name, code, bigCode='',
@@ -314,3 +326,15 @@
mnemonic = "tia"
microops["tia"] = TiaOp
+
+class LdioOp(LdStIoOp):
+ className = "Ldio"
+ mnemonic = "ldio"
+
+microops["ldio"] = LdioOp
+
+class StioOp(LdStIoOp):
+ className = "Stio"
+ mnemonic = "stio"
+
+microops["stio"] = StioOp
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index a0cac21..c193341 100644
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -57,9 +57,6 @@
constexpr int NumSegments = 6;
constexpr int NumSysSegments = 4;
-constexpr Addr IntAddrPrefixMask = 0xffffffff00000000ULL;
-constexpr Addr IntAddrPrefixIO = 0x300000000ULL;
-
constexpr Addr PhysAddrPrefixIO = 0x8000000000000000ULL;
constexpr Addr PhysAddrPrefixLocalAPIC = 0x2000000000000000ULL;
constexpr Addr PhysAddrPrefixInterrupts = 0xA000000000000000ULL;
--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: Ib1b7c13c58a9a70c1290bbee3229bcb532a45afe
Gerrit-Change-Number: 57019
Gerrit-PatchSet: 1
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