[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Generalize the RegOp operands.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42345 )
Change subject: arch-x86: Generalize the RegOp operands.
..
arch-x86: Generalize the RegOp operands.
This mechanism can now be used in other types of microops.
Change-Id: I82cb15b9d7b3c1e684aaa7482ea98b313f1d85d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42345
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
A src/arch/x86/insts/microop_args.hh
M src/arch/x86/insts/microregop.hh
M src/arch/x86/isa/microops/regop.isa
3 files changed, 223 insertions(+), 172 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/insts/microop_args.hh
b/src/arch/x86/insts/microop_args.hh
new file mode 100644
index 000..27af296
--- /dev/null
+++ b/src/arch/x86/insts/microop_args.hh
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2021 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_X86_INSTS_MICROOP_ARGS_HH__
+#define __ARCH_X86_INSTS_MICROOP_ARGS_HH__
+
+#include
+#include
+#include
+
+#include "arch/x86/insts/static_inst.hh"
+#include "arch/x86/regs/int.hh"
+#include "arch/x86/types.hh"
+#include "base/cprintf.hh"
+#include "cpu/reg_class.hh"
+
+namespace X86ISA
+{
+
+struct DestOp
+{
+using ArgType = InstRegIndex;
+const RegIndex dest;
+const size_t size;
+RegIndex index() const { return dest; }
+
+DestOp(RegIndex _dest, size_t _size) : dest(_dest), size(_size) {}
+};
+
+struct Src1Op
+{
+using ArgType = InstRegIndex;
+const RegIndex src1;
+const size_t size;
+RegIndex index() const { return src1; }
+
+Src1Op(RegIndex _src1, size_t _size) : src1(_src1), size(_size) {}
+};
+
+struct Src2Op
+{
+using ArgType = InstRegIndex;
+const RegIndex src2;
+const size_t size;
+RegIndex index() const { return src2; }
+
+Src2Op(RegIndex _src2, size_t _size) : src2(_src2), size(_size) {}
+};
+
+template
+struct FoldedOp : public Base
+{
+template
+FoldedOp(InstType *inst, typename Base::ArgType idx) :
+Base(INTREG_FOLDED(idx.index(), inst->foldOBit), inst->dataSize)
+{}
+
+void
+print(std::ostream ) const
+{
+X86StaticInst::printReg(os, RegId(IntRegClass, this->index()),
+this->size);
+}
+};
+
+template
+struct CrOp : public Base
+{
+template
+CrOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(),
0) {}
+
+void
+print(std::ostream ) const
+{
+ccprintf(os, "cr%d", this->index());
+}
+};
+
+template
+struct DbgOp : public Base
+{
+template
+DbgOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(),
0) {}
+
+void
+print(std::ostream ) const
+{
+ccprintf(os, "dr%d", this->index());
+}
+
+};
+
+template
+struct SegOp : public Base
+{
+template
+SegOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(),
0) {}
+
+void
+print(std::ostream ) const
+{
+X86StaticInst::printSegment(os, this->index());
+}
+};
+
+template
+struct MiscOp : public Base
+{
+template
+MiscOp(InstType *inst, typename Base::ArgType idx) :
+Base(idx.index(), inst->dataSize)
+{}
+
+void
+print(std::ostream ) const
+{
+X86StaticInst::printReg(os, RegId(MiscRegClass, this->index()),
+
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Generalize the RegOp operands.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42345 )
Change subject: arch-x86: Generalize the RegOp operands.
..
arch-x86: Generalize the RegOp operands.
This mechanism can now be used in other types of microops.
Change-Id: I82cb15b9d7b3c1e684aaa7482ea98b313f1d85d9
---
A src/arch/x86/insts/microop_args.hh
M src/arch/x86/insts/microregop.hh
M src/arch/x86/isa/microops/regop.isa
3 files changed, 223 insertions(+), 172 deletions(-)
diff --git a/src/arch/x86/insts/microop_args.hh
b/src/arch/x86/insts/microop_args.hh
new file mode 100644
index 000..27af296
--- /dev/null
+++ b/src/arch/x86/insts/microop_args.hh
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2021 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_X86_INSTS_MICROOP_ARGS_HH__
+#define __ARCH_X86_INSTS_MICROOP_ARGS_HH__
+
+#include
+#include
+#include
+
+#include "arch/x86/insts/static_inst.hh"
+#include "arch/x86/regs/int.hh"
+#include "arch/x86/types.hh"
+#include "base/cprintf.hh"
+#include "cpu/reg_class.hh"
+
+namespace X86ISA
+{
+
+struct DestOp
+{
+using ArgType = InstRegIndex;
+const RegIndex dest;
+const size_t size;
+RegIndex index() const { return dest; }
+
+DestOp(RegIndex _dest, size_t _size) : dest(_dest), size(_size) {}
+};
+
+struct Src1Op
+{
+using ArgType = InstRegIndex;
+const RegIndex src1;
+const size_t size;
+RegIndex index() const { return src1; }
+
+Src1Op(RegIndex _src1, size_t _size) : src1(_src1), size(_size) {}
+};
+
+struct Src2Op
+{
+using ArgType = InstRegIndex;
+const RegIndex src2;
+const size_t size;
+RegIndex index() const { return src2; }
+
+Src2Op(RegIndex _src2, size_t _size) : src2(_src2), size(_size) {}
+};
+
+template
+struct FoldedOp : public Base
+{
+template
+FoldedOp(InstType *inst, typename Base::ArgType idx) :
+Base(INTREG_FOLDED(idx.index(), inst->foldOBit), inst->dataSize)
+{}
+
+void
+print(std::ostream ) const
+{
+X86StaticInst::printReg(os, RegId(IntRegClass, this->index()),
+this->size);
+}
+};
+
+template
+struct CrOp : public Base
+{
+template
+CrOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(),
0) {}
+
+void
+print(std::ostream ) const
+{
+ccprintf(os, "cr%d", this->index());
+}
+};
+
+template
+struct DbgOp : public Base
+{
+template
+DbgOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(),
0) {}
+
+void
+print(std::ostream ) const
+{
+ccprintf(os, "dr%d", this->index());
+}
+
+};
+
+template
+struct SegOp : public Base
+{
+template
+SegOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(),
0) {}
+
+void
+print(std::ostream ) const
+{
+X86StaticInst::printSegment(os, this->index());
+}
+};
+
+template
+struct MiscOp : public Base
+{
+template
+MiscOp(InstType *inst, typename Base::ArgType idx) :
+Base(idx.index(), inst->dataSize)
+{}
+
+void
+print(std::ostream ) const
+{
+X86StaticInst::printReg(os, RegId(MiscRegClass, this->index()),
+this->size);
+}
+};
+
+using FoldedDestOp = FoldedOp;
+using DbgDestOp = DbgOp;
+using CrDestOp = CrOp;
+using SegDestOp = SegOp;
+using MiscDestOp = MiscOp;
+
+using FoldedSrc1Op = FoldedOp;
+using DbgSrc1Op = DbgOp;
+using CrSrc1Op
