Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57011 )
Change subject: arch-x86: Handle MSRs with rdmsr/wrmsr microops.
......................................................................
arch-x86: Handle MSRs with rdmsr/wrmsr microops.
MSRs are accessed with address-like indexes which map from a 32 bit
space down to the actual registers, but they are not actually loads or
stores in that they can't be accessed partially, or offset, or interact
with other loads/stores. It's much simpler to just map the MSR index to
a MiscReg index and then use the TC's readMiscReg and writeMiscReg
accessors.
Change-Id: I911bc54f5b7228af20a930234b34651a0042298d
---
M src/arch/amdgpu/common/tlb.cc
M src/arch/x86/isa/includes.isa
M src/arch/x86/microcode/system/msrs.ucode
M src/arch/x86/tlb.cc
M src/arch/x86/ucasmlib/arch/x86/microops/regop.py
M src/arch/x86/x86_traits.hh
6 files changed, 43 insertions(+), 38 deletions(-)
diff --git a/src/arch/amdgpu/common/tlb.cc b/src/arch/amdgpu/common/tlb.cc
index 0a00185..127aa02 100644
--- a/src/arch/amdgpu/common/tlb.cc
+++ b/src/arch/amdgpu/common/tlb.cc
@@ -303,22 +303,7 @@
Addr vaddr = req->getVaddr();
Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
- if (prefix == IntAddrPrefixMSR) {
- vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
-
- MiscRegIndex regNum;
- if (!msrAddrToIndex(regNum, vaddr))
- return std::make_shared<GeneralProtection>(0);
-
- req->setLocalAccessor(
- [read,regNum](ThreadContext *tc, PacketPtr pkt)
- {
- return localMiscRegAccess(read, regNum, tc, pkt);
- }
- );
-
- return NoFault;
- } else if (prefix == IntAddrPrefixIO) {
+ if (prefix == IntAddrPrefixIO) {
// TODO If CPL > IOPL or in virtual mode, check the I/O
permission
// bitmap in the TSS.
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 387319b..56b2f4c 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -117,6 +117,7 @@
#include "arch/x86/memhelpers.hh"
#include "arch/x86/pseudo_inst_abi.hh"
#include "arch/x86/regs/misc.hh"
+#include "arch/x86/regs/msr.hh"
#include "arch/x86/tlb.hh"
#include "base/compiler.hh"
#include "base/condcodes.hh"
diff --git a/src/arch/x86/microcode/system/msrs.ucode
b/src/arch/x86/microcode/system/msrs.ucode
index 3ea64d3..deba922 100644
--- a/src/arch/x86/microcode/system/msrs.ucode
+++ b/src/arch/x86/microcode/system/msrs.ucode
@@ -38,8 +38,7 @@
def macroop RDMSR
{
- ld t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
- dataSize=8, addressSize=8
+ rdmsr t2, rcx
mov rax, rax, t2, dataSize=4
srli t2, t2, 32, dataSize=8
mov rdx, rdx, t2, dataSize=4
@@ -51,8 +50,7 @@
mov t2, t2, rax, dataSize=4
slli t3, rdx, 32, dataSize=8
or t2, t2, t3, dataSize=8
- st t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
- dataSize=8, addressSize=8
+ wrmsr rcx, t2
};
def macroop RDTSC
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 024f880..0db17e5 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -200,23 +200,7 @@
DPRINTF(TLB, "Addresses references internal memory.\n");
Addr vaddr = req->getVaddr();
Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
- if (prefix == IntAddrPrefixMSR) {
- vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
-
- MiscRegIndex regNum;
- if (!msrAddrToIndex(regNum, vaddr))
- return std::make_shared<GeneralProtection>(0);
-
- req->setPaddr(req->getVaddr());
- req->setLocalAccessor(
- [read,regNum](ThreadContext *tc, PacketPtr pkt)
- {
- return localMiscRegAccess(read, regNum, tc, pkt);
- }
- );
-
- return NoFault;
- } else if (prefix == IntAddrPrefixIO) {
+ if (prefix == IntAddrPrefixIO) {
// TODO If CPL > IOPL or in virtual mode, check the I/O permission
// bitmap in the TSS.
diff --git a/src/arch/x86/ucasmlib/arch/x86/microops/regop.py
b/src/arch/x86/ucasmlib/arch/x86/microops/regop.py
index bca98e4..52c9ddf 100644
--- a/src/arch/x86/ucasmlib/arch/x86/microops/regop.py
+++ b/src/arch/x86/ucasmlib/arch/x86/microops/regop.py
@@ -1097,6 +1097,28 @@
"DestReg = merge(DestReg, dest, ControlSrc1, dataSize);"
big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);"
+class Wrmsr(RegOp):
+ operand_types = (IntSrc1Op, IntSrc2Op)
+ def __init__(self, msr_num, src):
+ super().__init__(msr_num, src, flags=None, dataSize='8')
+ code = '''
+ MiscRegIndex reg_num;
+ if (!X86ISA::msrAddrToIndex(reg_num, SrcReg1 & mask(32)))
+ return std::make_shared<GeneralProtection>(0);
+ xc->tcBase()->setMiscReg(reg_num, SrcReg2);
+ '''
+
+class Rdmsr(RegOp):
+ operand_types = (IntDestOp, IntSrc1Op)
+ def __init__(self, dest, msr_num):
+ super().__init__(dest, msr_num, flags=None, dataSize='8')
+ code = '''
+ MiscRegIndex reg_num;
+ if (!X86ISA::msrAddrToIndex(reg_num, SrcReg1))
+ return std::make_shared<GeneralProtection>(0);
+ DestReg = xc->tcBase()->readMiscReg(reg_num);
+ '''
+
class Wrcr(RegOp):
operand_types = (CrDestOp, FoldedSrc1Op)
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index 71c4c87..71d0929 100644
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -60,7 +60,6 @@
const int NumSysSegments = 4;
const Addr IntAddrPrefixMask = 0xffffffff00000000ULL;
- const Addr IntAddrPrefixMSR = 0x200000000ULL;
const Addr IntAddrPrefixIO = 0x300000000ULL;
const Addr PhysAddrPrefixIO = 0x8000000000000000ULL;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I911bc54f5b7228af20a930234b34651a0042298d
Gerrit-Change-Number: 57011
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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