[gem5-dev] Change in gem5/gem5[develop]: base, sim, mem, arch: Remove the dummy CPU in NULL
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34236 )
Change subject: base, sim, mem, arch: Remove the dummy CPU in NULL
..
base, sim, mem, arch: Remove the dummy CPU in NULL
The NULL ISA target has a dummy BaseCPU class that doesn't seem to be
needed anymore. Remove this class and the some unnecessary includes.
Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34236
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Reviewed-by: Daniel Carvalho
Tested-by: kokoro
---
M src/arch/mips/locked_mem.hh
M src/arch/null/SConscript
D src/arch/null/cpu_dummy.cc
D src/arch/null/cpu_dummy.hh
M src/arch/riscv/locked_mem.hh
M src/cpu/base.hh
M src/mem/abstract_mem.cc
M src/mem/cache/prefetch/base.cc
M src/sim/stat_control.cc
M src/sim/system.cc
M src/sim/system.hh
11 files changed, 17 insertions(+), 102 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 8400ed6..153a991 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -50,6 +50,7 @@
#include "arch/registers.hh"
#include "base/logging.hh"
#include "base/trace.hh"
+#include "cpu/base.hh"
#include "debug/LLSC.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
diff --git a/src/arch/null/SConscript b/src/arch/null/SConscript
index 41457e2..3f0b053 100644
--- a/src/arch/null/SConscript
+++ b/src/arch/null/SConscript
@@ -36,6 +36,3 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
-
-if env['TARGET_ISA'] == 'null':
-Source('cpu_dummy.cc')
diff --git a/src/arch/null/cpu_dummy.cc b/src/arch/null/cpu_dummy.cc
deleted file mode 100644
index df30b81..000
--- a/src/arch/null/cpu_dummy.cc
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * Provide the actual storage for maxThreadsPerCPU which is declared
- * extern and normally provided by src/cpu/base.cc
- */
-int maxThreadsPerCPU = 1;
diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh
deleted file mode 100644
index 7e183eb..000
--- a/src/arch/null/cpu_dummy.hh
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- *
[gem5-dev] Change in gem5/gem5[develop]: base, sim, mem, arch: Remove the dummy CPU in NULL
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34236 )
Change subject: base, sim, mem, arch: Remove the dummy CPU in NULL
..
base, sim, mem, arch: Remove the dummy CPU in NULL
The NULL ISA target has a dummy BaseCPU class that doesn't seem to be
needed anymore. Remove this class and the some unnecessary includes.
Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501
Signed-off-by: Andreas Sandberg
---
M src/arch/null/SConscript
D src/arch/null/cpu_dummy.cc
D src/arch/null/cpu_dummy.hh
M src/cpu/base.hh
M src/mem/abstract_mem.cc
M src/mem/cache/prefetch/base.cc
M src/sim/stat_control.cc
M src/sim/system.cc
M src/sim/system.hh
9 files changed, 9 insertions(+), 100 deletions(-)
diff --git a/src/arch/null/SConscript b/src/arch/null/SConscript
index 41457e2..3f0b053 100644
--- a/src/arch/null/SConscript
+++ b/src/arch/null/SConscript
@@ -36,6 +36,3 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
-
-if env['TARGET_ISA'] == 'null':
-Source('cpu_dummy.cc')
diff --git a/src/arch/null/cpu_dummy.cc b/src/arch/null/cpu_dummy.cc
deleted file mode 100644
index df30b81..000
--- a/src/arch/null/cpu_dummy.cc
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * Provide the actual storage for maxThreadsPerCPU which is declared
- * extern and normally provided by src/cpu/base.cc
- */
-int maxThreadsPerCPU = 1;
diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh
deleted file mode 100644
index 7e183eb..000
--- a/src/arch/null/cpu_dummy.hh
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders
