[gem5-dev] Change in gem5/gem5[develop]: configs: Weed out old port terminology in Arm examples
Andreas Sandberg has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/39582 ) Change subject: configs: Weed out old port terminology in Arm examples .. configs: Weed out old port terminology in Arm examples Stop using the deprecated port names in Arm example scripts. Change-Id: I11fea3e0df945ac64075b647766570604b70cad8 Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39582 Reviewed-by: Gabe Black Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M configs/common/MemConfig.py M configs/example/arm/devices.py M configs/example/arm/fs_bigLITTLE.py M configs/example/arm/starter_se.py 4 files changed, 20 insertions(+), 19 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py index 63301ab..94b1655 100644 --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -151,7 +151,7 @@ system.external_memory = m5.objects.ExternalSlave( port_type="tlm_slave", port_data=opt_tlm_memory, -port=system.membus.master, +port=system.membus.mem_side_ports, addr_ranges=system.mem_ranges) system.workload.addr_check = False return @@ -269,12 +269,12 @@ for i in range(len(mem_ctrls)): if opt_mem_type == "HMC_2500_1x32": # Connect the controllers to the membus -mem_ctrls[i].port = xbar[i/4].master +mem_ctrls[i].port = xbar[i/4].mem_side_ports # Set memory device size. There is an independent controller # for each vault. All vaults are same size. mem_ctrls[i].dram.device_size = options.hmc_dev_vault_size else: # Connect the controllers to the membus -mem_ctrls[i].port = xbar.master +mem_ctrls[i].port = xbar.mem_side_ports subsystem.mem_ctrls = mem_ctrls diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py index 52613c6..9ef4d70 100644 --- a/configs/example/arm/devices.py +++ b/configs/example/arm/devices.py @@ -151,7 +151,7 @@ self.l2 = self._l2_type() for cpu in self.cpus: cpu.connectAllPorts(self.toL2Bus) -self.toL2Bus.master = self.l2.cpu_side +self.toL2Bus.mem_side_ports = self.l2.cpu_side def addPMUs(self, ints, events=[]): """ @@ -181,7 +181,7 @@ def connectMemSide(self, bus): try: -self.l2.mem_side = bus.slave +self.l2.mem_side = bus.cpu_side_ports except AttributeError: for cpu in self.cpus: cpu.connectAllPorts(bus) @@ -223,8 +223,9 @@ ]) gic_a2t = AmbaToTlmBridge64(amba=gic.amba_m) -gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm, gem5=system.iobus.slave) -gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.master) +gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm, +gem5=system.iobus.cpu_side_ports) +gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.mem_side_ports) gic_g2t.addr_ranges = gic.get_addr_ranges() gic_t2a = AmbaFromTlmBridge64(tlm=gic_g2t.tlm) gic.amba_s = gic_t2a.amba @@ -255,7 +256,7 @@ self.cpus = [ cpu ] a2t = AmbaToTlmBridge64(amba=cpu.amba) -t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.slave) +t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.cpu_side_ports) system.gic_hub.a2t = a2t system.gic_hub.t2g = t2g @@ -330,21 +331,21 @@ self.realview.attachPciDevice(dev, self.iobus) def connect(self): -self.iobridge.master = self.iobus.slave -self.iobridge.slave = self.membus.master +self.iobridge.mem_side_port = self.iobus.cpu_side_ports +self.iobridge.cpu_side_port = self.membus.mem_side_ports if self._caches: -self.iocache.mem_side = self.membus.slave -self.iocache.cpu_side = self.iobus.master +self.iocache.mem_side = self.membus.cpu_side_ports +self.iocache.cpu_side = self.iobus.mem_side_ports else: -self.dmabridge.master = self.membus.slave -self.dmabridge.slave = self.iobus.master +self.dmabridge.mem_side_port = self.membus.cpu_side_ports +self.dmabridge.cpu_side_port = self.iobus.mem_side_ports if hasattr(self.realview.gic, 'cpu_addr'): self.gic_cpu_addr = self.realview.gic.cpu_addr self.realview.attachOnChipIO(self.membus, self.iobridge) self.realview.attachIO(self.iobus) -self.
[gem5-dev] Change in gem5/gem5[develop]: configs: Weed out old port terminology in Arm examples
Andreas Sandberg has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/39582 ) Change subject: configs: Weed out old port terminology in Arm examples .. configs: Weed out old port terminology in Arm examples Stop using the deprecated port names in Arm example scripts. Change-Id: I11fea3e0df945ac64075b647766570604b70cad8 Signed-off-by: Andreas Sandberg --- M configs/common/MemConfig.py M configs/example/arm/devices.py M configs/example/arm/fs_bigLITTLE.py M configs/example/arm/starter_se.py 4 files changed, 20 insertions(+), 19 deletions(-) diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py index 63301ab..94b1655 100644 --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -151,7 +151,7 @@ system.external_memory = m5.objects.ExternalSlave( port_type="tlm_slave", port_data=opt_tlm_memory, -port=system.membus.master, +port=system.membus.mem_side_ports, addr_ranges=system.mem_ranges) system.workload.addr_check = False return @@ -269,12 +269,12 @@ for i in range(len(mem_ctrls)): if opt_mem_type == "HMC_2500_1x32": # Connect the controllers to the membus -mem_ctrls[i].port = xbar[i/4].master +mem_ctrls[i].port = xbar[i/4].mem_side_ports # Set memory device size. There is an independent controller # for each vault. All vaults are same size. mem_ctrls[i].dram.device_size = options.hmc_dev_vault_size else: # Connect the controllers to the membus -mem_ctrls[i].port = xbar.master +mem_ctrls[i].port = xbar.mem_side_ports subsystem.mem_ctrls = mem_ctrls diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py index 52613c6..9ef4d70 100644 --- a/configs/example/arm/devices.py +++ b/configs/example/arm/devices.py @@ -151,7 +151,7 @@ self.l2 = self._l2_type() for cpu in self.cpus: cpu.connectAllPorts(self.toL2Bus) -self.toL2Bus.master = self.l2.cpu_side +self.toL2Bus.mem_side_ports = self.l2.cpu_side def addPMUs(self, ints, events=[]): """ @@ -181,7 +181,7 @@ def connectMemSide(self, bus): try: -self.l2.mem_side = bus.slave +self.l2.mem_side = bus.cpu_side_ports except AttributeError: for cpu in self.cpus: cpu.connectAllPorts(bus) @@ -223,8 +223,9 @@ ]) gic_a2t = AmbaToTlmBridge64(amba=gic.amba_m) -gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm, gem5=system.iobus.slave) -gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.master) +gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm, +gem5=system.iobus.cpu_side_ports) +gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.mem_side_ports) gic_g2t.addr_ranges = gic.get_addr_ranges() gic_t2a = AmbaFromTlmBridge64(tlm=gic_g2t.tlm) gic.amba_s = gic_t2a.amba @@ -255,7 +256,7 @@ self.cpus = [ cpu ] a2t = AmbaToTlmBridge64(amba=cpu.amba) -t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.slave) +t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.cpu_side_ports) system.gic_hub.a2t = a2t system.gic_hub.t2g = t2g @@ -330,21 +331,21 @@ self.realview.attachPciDevice(dev, self.iobus) def connect(self): -self.iobridge.master = self.iobus.slave -self.iobridge.slave = self.membus.master +self.iobridge.mem_side_port = self.iobus.cpu_side_ports +self.iobridge.cpu_side_port = self.membus.mem_side_ports if self._caches: -self.iocache.mem_side = self.membus.slave -self.iocache.cpu_side = self.iobus.master +self.iocache.mem_side = self.membus.cpu_side_ports +self.iocache.cpu_side = self.iobus.mem_side_ports else: -self.dmabridge.master = self.membus.slave -self.dmabridge.slave = self.iobus.master +self.dmabridge.mem_side_port = self.membus.cpu_side_ports +self.dmabridge.cpu_side_port = self.iobus.mem_side_ports if hasattr(self.realview.gic, 'cpu_addr'): self.gic_cpu_addr = self.realview.gic.cpu_addr self.realview.attachOnChipIO(self.membus, self.iobridge) self.realview.attachIO(self.iobus) -self.system_port = self.membus.slave +self.system_port = self.membus.cpu_side_ports def numCpuClusters(self): return len(self._clusters) @@ -377,8 +378,8 @@ key=lambda c: c.clk_domain.clock[0]) self.l3 = L3(clk_domain=max_clock_cl
