subject:"\[gem5\-dev\] Change in gem5\/gem5\[develop\]\: cpu\: update port terminology"

[gem5-dev] Change in gem5/gem5[develop]: cpu: update port terminology

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32312 )


Change subject: cpu: update port terminology
..

cpu: update port terminology

Change-Id: I891e7a74683c1775c75a62454fcfdecb7511b7e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32312
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
---
M src/cpu/BaseCPU.py
M src/cpu/base.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/kvm/base.hh
M src/cpu/minor/cpu.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/noncaching.cc
M src/cpu/simple/noncaching.hh
M src/cpu/simple/timing.hh
M src/cpu/testers/directedtest/InvalidateGenerator.cc
M src/cpu/testers/directedtest/RubyDirectedTester.cc
M src/cpu/testers/directedtest/RubyDirectedTester.hh
M src/cpu/testers/directedtest/SeriesRequestGenerator.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
M src/cpu/testers/memtest/MemTest.py
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/rubytest/Check.cc
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/rubytest/RubyTester.hh
M src/cpu/testers/traffic_gen/BaseTrafficGen.py
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/trace/trace_cpu.hh
29 files changed, 67 insertions(+), 67 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 96e96fc..ee6c646 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -175,8 +175,8 @@

 tracer = Param.InstTracer(default_tracer, "Instruction tracer")

-icache_port = MasterPort("Instruction Port")
-dcache_port = MasterPort("Data Port")
+icache_port = RequestPort("Instruction Port")
+dcache_port = RequestPort("Data Port")
 _cached_ports = ['icache_port', 'dcache_port']

 if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index a00e83d..5c0c709 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -162,7 +162,7 @@
 virtual PortProxy::SendFunctionalFunc
 getSendFunctional()
 {
-auto port = dynamic_cast(());
+auto port = dynamic_cast(());
 assert(port);
 return [port](PacketPtr pkt)->void { port->sendFunctional(pkt); };
 }
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index d9d6d7e..b016938 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -113,13 +113,13 @@
 }

 void
-CheckerCPU::setIcachePort(MasterPort *icache_port)
+CheckerCPU::setIcachePort(RequestPort *icache_port)
 {
 icachePort = icache_port;
 }

 void
-CheckerCPU::setDcachePort(MasterPort *dcache_port)
+CheckerCPU::setDcachePort(RequestPort *dcache_port)
 {
 dcachePort = dcache_port;
 }
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 6bd7022..3c04064 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -99,9 +99,9 @@

 void setSystem(System *system);

-void setIcachePort(MasterPort *icache_port);
+void setIcachePort(RequestPort *icache_port);

-void setDcachePort(MasterPort *dcache_port);
+void setDcachePort(RequestPort *dcache_port);

 Port &
 getDataPort() override
@@ -127,8 +127,8 @@

 System *systemPtr;

-MasterPort *icachePort;
-MasterPort *dcachePort;
+RequestPort *icachePort;
+RequestPort *dcachePort;

 ThreadContext *tc;

diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index eff7a3c..e999499 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -572,15 +572,15 @@


 /**
- * KVM memory port.  Uses default MasterPort behavior and provides an
+ * KVM memory port.  Uses default RequestPort behavior and provides an
  * interface for KVM to transparently submit atomic or timing requests.
  */
-class KVMCpuPort : public MasterPort
+class KVMCpuPort : public RequestPort
 {

   public:
 KVMCpuPort(const std::string &_name, BaseKvmCPU *_cpu)
-: MasterPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
+: RequestPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
 { }
 /**
  * Interface to send Atomic or Timing IO request.  Assumes that  
the pkt

diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index b8ca087..579a96b 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -95,7 +95,7 @@
   public:
 /** Provide a non-protected base class for Minor's Ports as derived
  *  classes are created by Fetch1 and Execute */
-class MinorCPUPort : public MasterPort
+class MinorCPUPort : public RequestPort
 {
   public:
 /** The enclosing cpu */
@@

[gem5-dev] Change in gem5/gem5[develop]: cpu: update port terminology

2020-08-06 Thread Shivani Parekh (Gerrit) via gem5-dev


Hello Emily Brickey,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/32312

to review the following change.


Change subject: cpu: update port terminology
..

cpu: update port terminology

Change-Id: I891e7a74683c1775c75a62454fcfdecb7511b7e9
---
M src/cpu/BaseCPU.py
M src/cpu/base.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/kvm/base.hh
M src/cpu/minor/cpu.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/noncaching.cc
M src/cpu/simple/noncaching.hh
M src/cpu/simple/timing.hh
M src/cpu/testers/directedtest/InvalidateGenerator.cc
M src/cpu/testers/directedtest/RubyDirectedTester.cc
M src/cpu/testers/directedtest/RubyDirectedTester.hh
M src/cpu/testers/directedtest/SeriesRequestGenerator.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
M src/cpu/testers/memtest/MemTest.py
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/rubytest/Check.cc
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/rubytest/RubyTester.hh
M src/cpu/testers/traffic_gen/BaseTrafficGen.py
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/trace/trace_cpu.hh
29 files changed, 67 insertions(+), 67 deletions(-)



diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index e487cbb..5d47f4c 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -177,8 +177,8 @@

 tracer = Param.InstTracer(default_tracer, "Instruction tracer")

-icache_port = MasterPort("Instruction Port")
-dcache_port = MasterPort("Data Port")
+icache_port = RequestPort("Instruction Port")
+dcache_port = RequestPort("Data Port")
 _cached_ports = ['icache_port', 'dcache_port']

 if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index b9456a9..51dd6be 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -163,7 +163,7 @@
 virtual PortProxy::SendFunctionalFunc
 getSendFunctional()
 {
-auto port = dynamic_cast(());
+auto port = dynamic_cast(());
 assert(port);
 return [port](PacketPtr pkt)->void { port->sendFunctional(pkt); };
 }
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index d9d6d7e..b016938 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -113,13 +113,13 @@
 }

 void
-CheckerCPU::setIcachePort(MasterPort *icache_port)
+CheckerCPU::setIcachePort(RequestPort *icache_port)
 {
 icachePort = icache_port;
 }

 void
-CheckerCPU::setDcachePort(MasterPort *dcache_port)
+CheckerCPU::setDcachePort(RequestPort *dcache_port)
 {
 dcachePort = dcache_port;
 }
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 6bd7022..3c04064 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -99,9 +99,9 @@

 void setSystem(System *system);

-void setIcachePort(MasterPort *icache_port);
+void setIcachePort(RequestPort *icache_port);

-void setDcachePort(MasterPort *dcache_port);
+void setDcachePort(RequestPort *dcache_port);

 Port &
 getDataPort() override
@@ -127,8 +127,8 @@

 System *systemPtr;

-MasterPort *icachePort;
-MasterPort *dcachePort;
+RequestPort *icachePort;
+RequestPort *dcachePort;

 ThreadContext *tc;

diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index eff7a3c..e999499 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -572,15 +572,15 @@


 /**
- * KVM memory port.  Uses default MasterPort behavior and provides an
+ * KVM memory port.  Uses default RequestPort behavior and provides an
  * interface for KVM to transparently submit atomic or timing requests.
  */
-class KVMCpuPort : public MasterPort
+class KVMCpuPort : public RequestPort
 {

   public:
 KVMCpuPort(const std::string &_name, BaseKvmCPU *_cpu)
-: MasterPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
+: RequestPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
 { }
 /**
  * Interface to send Atomic or Timing IO request.  Assumes that  
the pkt

diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index b8ca087..579a96b 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -95,7 +95,7 @@
   public:
 /** Provide a non-protected base class for Minor's Ports as derived
  *  classes are created by Fetch1 and Execute */
-class MinorCPUPort : public MasterPort
+class MinorCPUPort : public RequestPort
 {
   public:
 /** The enclosing cpu */
@@ -103,7 +103,7 @@

   public:
 MinorCPUPort(const std::string& name_, MinorCPU _)
-: MasterPort(name_, _), cpu(cpu_)
+: RequestPort(name_, _), cpu(cpu_)
 { }

 };
diff --git

[gem5-dev] Change in gem5/gem5[develop]: cpu: update port terminology

[gem5-dev] Change in gem5/gem5[develop]: cpu: update port terminology

2 matches

Site Navigation

Mail list logo

Footer information