[gem5-dev] Change in gem5/gem5[develop]: dev: Update port terminology
Shivani Parekh has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/32315 ) Change subject: dev: Update port terminology .. dev: Update port terminology Change-Id: I48bd6718471f034f7c3226279efe7ada0d9c81e9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32315 Reviewed-by: Giacomo Travaglini Reviewed-by: Gabe Black Maintainer: Giacomo Travaglini Maintainer: Gabe Black Tested-by: kokoro --- M src/dev/Device.py M src/dev/arm/Gic.py M src/dev/arm/SMMUv3.py M src/dev/arm/gic_v3_its.hh M src/dev/arm/smmu_v3_ports.cc M src/dev/arm/smmu_v3_ports.hh M src/dev/dma_device.cc M src/dev/dma_device.hh M src/dev/x86/I82094AA.py 9 files changed, 19 insertions(+), 18 deletions(-) Approvals: Gabe Black: Looks good to me, but someone else must approve; Looks good to me, approved Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/dev/Device.py b/src/dev/Device.py index 8950763..d9f351d 100644 --- a/src/dev/Device.py +++ b/src/dev/Device.py @@ -46,7 +46,7 @@ type = 'PioDevice' cxx_header = "dev/io_device.hh" abstract = True -pio = SlavePort("Programmed I/O port") +pio = ResponsePort("Programmed I/O port") system = Param.System(Parent.any, "System this device is part of") def generateBasicPioDeviceNode(self, state, name, pio_addr, @@ -79,7 +79,7 @@ type = 'DmaDevice' cxx_header = "dev/dma_device.hh" abstract = True -dma = MasterPort("DMA port") +dma = RequestPort("DMA port") _iommu = None diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py index 59ade75..e2229b8 100644 --- a/src/dev/arm/Gic.py +++ b/src/dev/arm/Gic.py @@ -177,7 +177,7 @@ type = 'Gicv3Its' cxx_header = "dev/arm/gic_v3_its.hh" -dma = MasterPort("DMA port") +dma = RequestPort("DMA port") pio_size = Param.Unsigned(0x2, "Gicv3Its pio size") # CIL [36] = 0: ITS supports 16-bit CollectionID diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py index 5be09de..0b9ab21 100644 --- a/src/dev/arm/SMMUv3.py +++ b/src/dev/arm/SMMUv3.py @@ -43,9 +43,9 @@ type = 'SMMUv3SlaveInterface' cxx_header = 'dev/arm/smmu_v3_slaveifc.hh' -slave = SlavePort('Device port') -ats_master = MasterPort('ATS master port') -ats_slave = SlavePort('ATS slave port') +slave = ResponsePort('Device port') +ats_master = RequestPort('ATS master port') +ats_slave = ResponsePort('ATS slave port') port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)') wrbuf_slots = Param.Unsigned(16, 'Write buffer size (in beats)') @@ -74,10 +74,11 @@ type = 'SMMUv3' cxx_header = 'dev/arm/smmu_v3.hh' -master = MasterPort('Master port') -master_walker = MasterPort( +master = RequestPort('Master port') +master_walker = RequestPort( 'Master port for SMMU initiated HWTW requests (optional)') -control = SlavePort('Control port for accessing memory-mapped registers') +control = ResponsePort( +'Control port for accessing memory-mapped registers') sample_period = Param.Clock('10us', 'Stats sample period') reg_map = Param.AddrRange('Address range for control registers') system = Param.System(Parent.any, "System this device is part of") diff --git a/src/dev/arm/gic_v3_its.hh b/src/dev/arm/gic_v3_its.hh index 8575f7e..54beb3e 100644 --- a/src/dev/arm/gic_v3_its.hh +++ b/src/dev/arm/gic_v3_its.hh @@ -77,14 +77,14 @@ friend class ::ItsTranslation; friend class ::ItsCommand; public: -class DataPort : public MasterPort +class DataPort : public RequestPort { protected: Gicv3Its &its; public: DataPort(const std::string &_name, Gicv3Its &_its) : -MasterPort(_name, &_its), +RequestPort(_name, &_its), its(_its) {} diff --git a/src/dev/arm/smmu_v3_ports.cc b/src/dev/arm/smmu_v3_ports.cc index f972fcf..3f54250 100644 --- a/src/dev/arm/smmu_v3_ports.cc +++ b/src/dev/arm/smmu_v3_ports.cc @@ -42,7 +42,7 @@ #include "dev/arm/smmu_v3_slaveifc.hh" SMMUMasterPort::SMMUMasterPort(const std::string &_name, SMMUv3 &_smmu) : -MasterPort(_name, &_smmu), +RequestPort(_name, &_smmu), smmu(_smmu) {} @@ -60,7 +60,7 @@ SMMUMasterTableWalkPort::SMMUMasterTableWalkPort(const std::string &_name, SMMUv3 &_smmu) : -MasterPort(_name, &_smmu), +RequestPort(_name, &_smmu), smmu(_smmu) {} diff --git a/src/dev/arm/smmu_v3_ports.hh b/src/dev/arm/smmu_v3_ports.hh index 9d54f13..ee68bbb 100644 --- a/src/dev/arm/smmu_v3_ports.hh +++ b/src/dev/arm/smmu_v3_ports.hh @@ -44,7 +44,7 @@ class SMMUv3; class SMMUv3SlaveInterface; -class SMMUMasterPort : public MasterPort +class SMMUMasterPort : public RequestPort { protected: SMMUv3 &smmu; @@ -58,7 +58,7 @
[gem5-dev] Change in gem5/gem5[develop]: dev: Update port terminology
Shivani Parekh has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/32315 ) Change subject: dev: Update port terminology .. dev: Update port terminology Change-Id: I48bd6718471f034f7c3226279efe7ada0d9c81e9 --- M src/dev/Device.py M src/dev/arm/Gic.py M src/dev/arm/SMMUv3.py M src/dev/arm/gic_v3_its.hh M src/dev/arm/smmu_v3_ports.cc M src/dev/arm/smmu_v3_ports.hh M src/dev/dma_device.cc M src/dev/dma_device.hh M src/dev/x86/I82094AA.py 9 files changed, 19 insertions(+), 18 deletions(-) diff --git a/src/dev/Device.py b/src/dev/Device.py index 8950763..d9f351d 100644 --- a/src/dev/Device.py +++ b/src/dev/Device.py @@ -46,7 +46,7 @@ type = 'PioDevice' cxx_header = "dev/io_device.hh" abstract = True -pio = SlavePort("Programmed I/O port") +pio = ResponsePort("Programmed I/O port") system = Param.System(Parent.any, "System this device is part of") def generateBasicPioDeviceNode(self, state, name, pio_addr, @@ -79,7 +79,7 @@ type = 'DmaDevice' cxx_header = "dev/dma_device.hh" abstract = True -dma = MasterPort("DMA port") +dma = RequestPort("DMA port") _iommu = None diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py index 59ade75..e2229b8 100644 --- a/src/dev/arm/Gic.py +++ b/src/dev/arm/Gic.py @@ -177,7 +177,7 @@ type = 'Gicv3Its' cxx_header = "dev/arm/gic_v3_its.hh" -dma = MasterPort("DMA port") +dma = RequestPort("DMA port") pio_size = Param.Unsigned(0x2, "Gicv3Its pio size") # CIL [36] = 0: ITS supports 16-bit CollectionID diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py index 5be09de..0b9ab21 100644 --- a/src/dev/arm/SMMUv3.py +++ b/src/dev/arm/SMMUv3.py @@ -43,9 +43,9 @@ type = 'SMMUv3SlaveInterface' cxx_header = 'dev/arm/smmu_v3_slaveifc.hh' -slave = SlavePort('Device port') -ats_master = MasterPort('ATS master port') -ats_slave = SlavePort('ATS slave port') +slave = ResponsePort('Device port') +ats_master = RequestPort('ATS master port') +ats_slave = ResponsePort('ATS slave port') port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)') wrbuf_slots = Param.Unsigned(16, 'Write buffer size (in beats)') @@ -74,10 +74,11 @@ type = 'SMMUv3' cxx_header = 'dev/arm/smmu_v3.hh' -master = MasterPort('Master port') -master_walker = MasterPort( +master = RequestPort('Master port') +master_walker = RequestPort( 'Master port for SMMU initiated HWTW requests (optional)') -control = SlavePort('Control port for accessing memory-mapped registers') +control = ResponsePort( +'Control port for accessing memory-mapped registers') sample_period = Param.Clock('10us', 'Stats sample period') reg_map = Param.AddrRange('Address range for control registers') system = Param.System(Parent.any, "System this device is part of") diff --git a/src/dev/arm/gic_v3_its.hh b/src/dev/arm/gic_v3_its.hh index 8575f7e..54beb3e 100644 --- a/src/dev/arm/gic_v3_its.hh +++ b/src/dev/arm/gic_v3_its.hh @@ -77,14 +77,14 @@ friend class ::ItsTranslation; friend class ::ItsCommand; public: -class DataPort : public MasterPort +class DataPort : public RequestPort { protected: Gicv3Its &its; public: DataPort(const std::string &_name, Gicv3Its &_its) : -MasterPort(_name, &_its), +RequestPort(_name, &_its), its(_its) {} diff --git a/src/dev/arm/smmu_v3_ports.cc b/src/dev/arm/smmu_v3_ports.cc index f972fcf..3f54250 100644 --- a/src/dev/arm/smmu_v3_ports.cc +++ b/src/dev/arm/smmu_v3_ports.cc @@ -42,7 +42,7 @@ #include "dev/arm/smmu_v3_slaveifc.hh" SMMUMasterPort::SMMUMasterPort(const std::string &_name, SMMUv3 &_smmu) : -MasterPort(_name, &_smmu), +RequestPort(_name, &_smmu), smmu(_smmu) {} @@ -60,7 +60,7 @@ SMMUMasterTableWalkPort::SMMUMasterTableWalkPort(const std::string &_name, SMMUv3 &_smmu) : -MasterPort(_name, &_smmu), +RequestPort(_name, &_smmu), smmu(_smmu) {} diff --git a/src/dev/arm/smmu_v3_ports.hh b/src/dev/arm/smmu_v3_ports.hh index 9d54f13..ee68bbb 100644 --- a/src/dev/arm/smmu_v3_ports.hh +++ b/src/dev/arm/smmu_v3_ports.hh @@ -44,7 +44,7 @@ class SMMUv3; class SMMUv3SlaveInterface; -class SMMUMasterPort : public MasterPort +class SMMUMasterPort : public RequestPort { protected: SMMUv3 &smmu; @@ -58,7 +58,7 @@ }; // Separate master port to send MMU initiated requests on -class SMMUMasterTableWalkPort : public MasterPort +class SMMUMasterTableWalkPort : public RequestPort { protected: SMMUv3 &smmu; diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc index 63642c9..03882e3 100644 --- a/src/dev/dma_device.cc +++ b/src/dev/dma_device.cc @@ -51,7 +51,7 @@ DmaPort::DmaPort(ClockedObject *d