[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexA76 fix missing registers for FastModel 11.17
Yu-hsin Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57629 )
Change subject: fastmodel: CortexA76 fix missing registers for FastModel
11.17
..
fastmodel: CortexA76 fix missing registers for FastModel 11.17
Change-Id: I1f6e2e92b91d0fe361a5ea88542a1e095a9f357b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57629
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
1 file changed, 64 insertions(+), 51 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
index ff82bbe..36c6458 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -267,7 +267,7 @@
{ ArmISA::MISCREG_DBGOSLAR, "DBGOSLAR" },
// ArmISA::MISCREG_DBGOSLSR?
// ArmISA::MISCREG_DBGOSDLR?
-{ ArmISA::MISCREG_DBGPRCR, "DBGPRCR_EL1" }, //XXX verify
+// ArmISA::MISCREG_DBGPRCR?
// ArmISA::MISCREG_DBGDSAR?
{ ArmISA::MISCREG_DBGCLAIMSET, "DBGCLAIMSET" },
{ ArmISA::MISCREG_DBGCLAIMCLR, "DBGCLAIMCLR" },
@@ -283,31 +283,31 @@
// AArch32 CP15 registers (system control)
{ ArmISA::MISCREG_MIDR, "MIDR" },
-{ ArmISA::MISCREG_CTR, "CTR" },
-{ ArmISA::MISCREG_TCMTR, "TCMTR" },
-{ ArmISA::MISCREG_TLBTR, "TLBTR" },
-{ ArmISA::MISCREG_MPIDR, "MPIDR" },
-{ ArmISA::MISCREG_REVIDR, "REVIDR" },
-{ ArmISA::MISCREG_ID_PFR0, "ID_PFR0" },
-{ ArmISA::MISCREG_ID_PFR1, "ID_PFR1" },
-{ ArmISA::MISCREG_ID_DFR0, "ID_DFR0" },
-{ ArmISA::MISCREG_ID_AFR0, "ID_AFR0" },
-{ ArmISA::MISCREG_ID_MMFR0, "ID_MMFR0" },
-{ ArmISA::MISCREG_ID_MMFR1, "ID_MMFR1" },
-{ ArmISA::MISCREG_ID_MMFR2, "ID_MMFR2" },
-{ ArmISA::MISCREG_ID_MMFR3, "ID_MMFR3" },
-{ ArmISA::MISCREG_ID_MMFR4, "ID_MMFR4" },
-{ ArmISA::MISCREG_ID_ISAR0, "ID_ISAR0" },
-{ ArmISA::MISCREG_ID_ISAR1, "ID_ISAR1" },
-{ ArmISA::MISCREG_ID_ISAR2, "ID_ISAR2" },
-{ ArmISA::MISCREG_ID_ISAR3, "ID_ISAR3" },
-{ ArmISA::MISCREG_ID_ISAR4, "ID_ISAR4" },
-{ ArmISA::MISCREG_ID_ISAR5, "ID_ISAR5" },
-{ ArmISA::MISCREG_ID_ISAR6, "ID_ISAR6" },
-{ ArmISA::MISCREG_CCSIDR, "CCSIDR" },
-{ ArmISA::MISCREG_CLIDR, "CLIDR" },
-{ ArmISA::MISCREG_AIDR, "AIDR" },
-{ ArmISA::MISCREG_CSSELR, "CSSELR_EL1" }, //XXX verify
+// ArmISA::MISCREG_CTR?
+// ArmISA::MISCREG_TCMTR?
+// ArmISA::MISCREG_TLBTR?
+// ArmISA::MISCREG_MPIDR?
+// ArmISA::MISCREG_REVIDR?
+// ArmISA::MISCREG_ID_PFR0?
+// ArmISA::MISCREG_ID_PFR1?
+// ArmISA::MISCREG_ID_DFR0?
+// ArmISA::MISCREG_ID_AFR0?
+// ArmISA::MISCREG_ID_MMFR0?
+// ArmISA::MISCREG_ID_MMFR1?
+// ArmISA::MISCREG_ID_MMFR2?
+// ArmISA::MISCREG_ID_MMFR3?
+// ArmISA::MISCREG_ID_MMFR4?
+// ArmISA::MISCREG_ID_ISAR0?
+// ArmISA::MISCREG_ID_ISAR1?
+// ArmISA::MISCREG_ID_ISAR2?
+// ArmISA::MISCREG_ID_ISAR3?
+// ArmISA::MISCREG_ID_ISAR4?
+// ArmISA::MISCREG_ID_ISAR5?
+// ArmISA::MISCREG_ID_ISAR6?
+// ArmISA::MISCREG_CCSIDR?
+// ArmISA::MISCREG_CLIDR?
+// ArmISA::MISCREG_AIDR?
+// ArmISA::MISCREG_CSSELR?
// ArmISA::MISCREG_CSSELR_NS?
// ArmISA::MISCREG_CSSELR_S?
// ArmISA::MISCREG_VPIDR?
@@ -327,7 +327,7 @@
// ArmISA::MISCREG_HCR?
// ArmISA::MISCREG_HDCR?
// ArmISA::MISCREG_HCPTR?
-{ ArmISA::MISCREG_HSTR, "HSTR_EL2" }, //XXX verify
+// ArmISA::MISCREG_HSTR?
// ArmISA::MISCREG_HACR?
// ArmISA::MISCREG_TTBR0?
// ArmISA::MISCREG_TTBR0_NS?
@@ -349,7 +349,7 @@
// ArmISA::MISCREG_IFSR?
// ArmISA::MISCREG_IFSR_NS?
// ArmISA::MISCREG_IFSR_S?
-// { ArmISA::MISCREG_ADFSR, "ADFSR" },
+// ArmISA::MISCREG_ADFSR?
// ArmISA::MISCREG_ADFSR_NS?
// ArmISA::MISCREG_ADFSR_S?
// ArmISA::MISCREG_AIFSR?
@@ -367,35 +367,35 @@
// ArmISA::MISCREG_HDFAR?
// ArmISA::MISCREG_HIFAR?
// ArmISA::MISCREG_HPFAR?
-{ ArmISA::MISCREG_ICIALLUIS, "ICIALLUIS" },
+// ArmISA::MISCREG_ICIALLUIS?
// ArmISA::MISCREG_BPIALLIS?
// ArmISA::MISCREG_PAR?
// ArmISA::MISCREG_PAR_NS?
// ArmISA::MISCREG_PAR_S?
-{ ArmISA::MISCREG_ICIALLU, "ICIALLU" },
-{ ArmISA::MISCREG_ICIMVAU, "ICIMVAU" },
+// ArmISA::MISCREG_ICIALLU?
+// ArmISA::MISCREG_ICIMVAU?
// ArmISA::MISCREG_CP15ISB?
[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexA76 fix missing registers for FastModel 11.17
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57629 )
Change subject: fastmodel: CortexA76 fix missing registers for FastModel
11.17
..
fastmodel: CortexA76 fix missing registers for FastModel 11.17
Change-Id: I1f6e2e92b91d0fe361a5ea88542a1e095a9f357b
---
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
1 file changed, 60 insertions(+), 51 deletions(-)
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
index ff82bbe..36c6458 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -267,7 +267,7 @@
{ ArmISA::MISCREG_DBGOSLAR, "DBGOSLAR" },
// ArmISA::MISCREG_DBGOSLSR?
// ArmISA::MISCREG_DBGOSDLR?
-{ ArmISA::MISCREG_DBGPRCR, "DBGPRCR_EL1" }, //XXX verify
+// ArmISA::MISCREG_DBGPRCR?
// ArmISA::MISCREG_DBGDSAR?
{ ArmISA::MISCREG_DBGCLAIMSET, "DBGCLAIMSET" },
{ ArmISA::MISCREG_DBGCLAIMCLR, "DBGCLAIMCLR" },
@@ -283,31 +283,31 @@
// AArch32 CP15 registers (system control)
{ ArmISA::MISCREG_MIDR, "MIDR" },
-{ ArmISA::MISCREG_CTR, "CTR" },
-{ ArmISA::MISCREG_TCMTR, "TCMTR" },
-{ ArmISA::MISCREG_TLBTR, "TLBTR" },
-{ ArmISA::MISCREG_MPIDR, "MPIDR" },
-{ ArmISA::MISCREG_REVIDR, "REVIDR" },
-{ ArmISA::MISCREG_ID_PFR0, "ID_PFR0" },
-{ ArmISA::MISCREG_ID_PFR1, "ID_PFR1" },
-{ ArmISA::MISCREG_ID_DFR0, "ID_DFR0" },
-{ ArmISA::MISCREG_ID_AFR0, "ID_AFR0" },
-{ ArmISA::MISCREG_ID_MMFR0, "ID_MMFR0" },
-{ ArmISA::MISCREG_ID_MMFR1, "ID_MMFR1" },
-{ ArmISA::MISCREG_ID_MMFR2, "ID_MMFR2" },
-{ ArmISA::MISCREG_ID_MMFR3, "ID_MMFR3" },
-{ ArmISA::MISCREG_ID_MMFR4, "ID_MMFR4" },
-{ ArmISA::MISCREG_ID_ISAR0, "ID_ISAR0" },
-{ ArmISA::MISCREG_ID_ISAR1, "ID_ISAR1" },
-{ ArmISA::MISCREG_ID_ISAR2, "ID_ISAR2" },
-{ ArmISA::MISCREG_ID_ISAR3, "ID_ISAR3" },
-{ ArmISA::MISCREG_ID_ISAR4, "ID_ISAR4" },
-{ ArmISA::MISCREG_ID_ISAR5, "ID_ISAR5" },
-{ ArmISA::MISCREG_ID_ISAR6, "ID_ISAR6" },
-{ ArmISA::MISCREG_CCSIDR, "CCSIDR" },
-{ ArmISA::MISCREG_CLIDR, "CLIDR" },
-{ ArmISA::MISCREG_AIDR, "AIDR" },
-{ ArmISA::MISCREG_CSSELR, "CSSELR_EL1" }, //XXX verify
+// ArmISA::MISCREG_CTR?
+// ArmISA::MISCREG_TCMTR?
+// ArmISA::MISCREG_TLBTR?
+// ArmISA::MISCREG_MPIDR?
+// ArmISA::MISCREG_REVIDR?
+// ArmISA::MISCREG_ID_PFR0?
+// ArmISA::MISCREG_ID_PFR1?
+// ArmISA::MISCREG_ID_DFR0?
+// ArmISA::MISCREG_ID_AFR0?
+// ArmISA::MISCREG_ID_MMFR0?
+// ArmISA::MISCREG_ID_MMFR1?
+// ArmISA::MISCREG_ID_MMFR2?
+// ArmISA::MISCREG_ID_MMFR3?
+// ArmISA::MISCREG_ID_MMFR4?
+// ArmISA::MISCREG_ID_ISAR0?
+// ArmISA::MISCREG_ID_ISAR1?
+// ArmISA::MISCREG_ID_ISAR2?
+// ArmISA::MISCREG_ID_ISAR3?
+// ArmISA::MISCREG_ID_ISAR4?
+// ArmISA::MISCREG_ID_ISAR5?
+// ArmISA::MISCREG_ID_ISAR6?
+// ArmISA::MISCREG_CCSIDR?
+// ArmISA::MISCREG_CLIDR?
+// ArmISA::MISCREG_AIDR?
+// ArmISA::MISCREG_CSSELR?
// ArmISA::MISCREG_CSSELR_NS?
// ArmISA::MISCREG_CSSELR_S?
// ArmISA::MISCREG_VPIDR?
@@ -327,7 +327,7 @@
// ArmISA::MISCREG_HCR?
// ArmISA::MISCREG_HDCR?
// ArmISA::MISCREG_HCPTR?
-{ ArmISA::MISCREG_HSTR, "HSTR_EL2" }, //XXX verify
+// ArmISA::MISCREG_HSTR?
// ArmISA::MISCREG_HACR?
// ArmISA::MISCREG_TTBR0?
// ArmISA::MISCREG_TTBR0_NS?
@@ -349,7 +349,7 @@
// ArmISA::MISCREG_IFSR?
// ArmISA::MISCREG_IFSR_NS?
// ArmISA::MISCREG_IFSR_S?
-// { ArmISA::MISCREG_ADFSR, "ADFSR" },
+// ArmISA::MISCREG_ADFSR?
// ArmISA::MISCREG_ADFSR_NS?
// ArmISA::MISCREG_ADFSR_S?
// ArmISA::MISCREG_AIFSR?
@@ -367,35 +367,35 @@
// ArmISA::MISCREG_HDFAR?
// ArmISA::MISCREG_HIFAR?
// ArmISA::MISCREG_HPFAR?
-{ ArmISA::MISCREG_ICIALLUIS, "ICIALLUIS" },
+// ArmISA::MISCREG_ICIALLUIS?
// ArmISA::MISCREG_BPIALLIS?
// ArmISA::MISCREG_PAR?
// ArmISA::MISCREG_PAR_NS?
// ArmISA::MISCREG_PAR_S?
-{ ArmISA::MISCREG_ICIALLU, "ICIALLU" },
-{ ArmISA::MISCREG_ICIMVAU, "ICIMVAU" },
+// ArmISA::MISCREG_ICIALLU?
+// ArmISA::MISCREG_ICIMVAU?
// ArmISA::MISCREG_CP15ISB?
// ArmISA::MISCREG_BPIALL?
// ArmISA::MISCREG_BPIMVA?
-{ ArmISA::MISCREG_DCIMVAC, "DCIMVAC" },
-{ ArmISA::MISCREG_DCISW, "DCISW" },
-{ ArmISA::MISCREG_ATS1CPR, "ATS1CPR" },
-{ ArmISA::MISCREG_A
