[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: update port terminology

[Shivani Parekh (Gerrit) via gem5-dev]

Shivani Parekh has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32310 )


Change subject: learning-gem5: update port terminology
..

learning-gem5: update port terminology

Change-Id: I0ca705cf93396b5c34a0ac4dce30411c5c866733
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32310
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/learning_gem5/part2/SimpleCache.py
M src/learning_gem5/part2/SimpleMemobj.py
M src/learning_gem5/part2/simple_cache.hh
M src/learning_gem5/part2/simple_memobj.hh
4 files changed, 22 insertions(+), 22 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/learning_gem5/part2/SimpleCache.py  
b/src/learning_gem5/part2/SimpleCache.py

index bd5ebfc..40892b5 100644
--- a/src/learning_gem5/part2/SimpleCache.py
+++ b/src/learning_gem5/part2/SimpleCache.py
@@ -36,7 +36,7 @@
 # Vector port example. Both the instruction and data ports connect to  
this

 # port which is automatically split out into two ports.
 cpu_side = VectorSlavePort("CPU side port, receives requests")
-mem_side = MasterPort("Memory side port, sends requests")
+mem_side = RequestPort("Memory side port, sends requests")

 latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss")

diff --git a/src/learning_gem5/part2/SimpleMemobj.py  
b/src/learning_gem5/part2/SimpleMemobj.py

index aee81c4..b72ebe2 100644
--- a/src/learning_gem5/part2/SimpleMemobj.py
+++ b/src/learning_gem5/part2/SimpleMemobj.py
@@ -32,6 +32,6 @@
 type = 'SimpleMemobj'
 cxx_header = "learning_gem5/part2/simple_memobj.hh"

-inst_port = SlavePort("CPU side port, receives requests")
-data_port = SlavePort("CPU side port, receives requests")
-mem_side = MasterPort("Memory side port, sends requests")
+inst_port = ResponsePort("CPU side port, receives requests")
+data_port = ResponsePort("CPU side port, receives requests")
+mem_side = RequestPort("Memory side port, sends requests")
diff --git a/src/learning_gem5/part2/simple_cache.hh  
b/src/learning_gem5/part2/simple_cache.hh

index dbc128b..4e57c87 100644
--- a/src/learning_gem5/part2/simple_cache.hh
+++ b/src/learning_gem5/part2/simple_cache.hh
@@ -51,7 +51,7 @@
  * Port on the CPU-side that receives requests.
  * Mostly just forwards requests to the cache (owner)
  */
-class CPUSidePort : public SlavePort
+class CPUSidePort : public ResponsePort
 {
   private:
 /// Since this is a vector port, need to know what number this one  
is

@@ -71,7 +71,7 @@
  * Constructor. Just calls the superclass constructor.
  */
 CPUSidePort(const std::string& name, int id, SimpleCache *owner) :
-SlavePort(name, owner), id(id), owner(owner), needRetry(false),
+ResponsePort(name, owner), id(id), owner(owner),  
needRetry(false),

 blockedPacket(nullptr)
 { }

@@ -137,7 +137,7 @@
  * Port on the memory-side that receives responses.
  * Mostly just forwards requests to the cache (owner)
  */
-class MemSidePort : public MasterPort
+class MemSidePort : public RequestPort
 {
   private:
 /// The object that owns this object (SimpleCache)
@@ -151,7 +151,7 @@
  * Constructor. Just calls the superclass constructor.
  */
 MemSidePort(const std::string& name, SimpleCache *owner) :
-MasterPort(name, owner), owner(owner), blockedPacket(nullptr)
+RequestPort(name, owner), owner(owner), blockedPacket(nullptr)
 { }

 /**
diff --git a/src/learning_gem5/part2/simple_memobj.hh  
b/src/learning_gem5/part2/simple_memobj.hh

index b7c57ca..11a4b36 100644
--- a/src/learning_gem5/part2/simple_memobj.hh
+++ b/src/learning_gem5/part2/simple_memobj.hh
@@ -48,7 +48,7 @@
  * Mostly just forwards requests to the owner.
  * Part of a vector of ports. One for each CPU port (e.g., data, inst)
  */
-class CPUSidePort : public SlavePort
+class CPUSidePort : public ResponsePort
 {
   private:
 /// The object that owns this object (SimpleMemobj)
@@ -65,7 +65,7 @@
  * Constructor. Just calls the superclass constructor.
  */
 CPUSidePort(const std::string& name, SimpleMemobj *owner) :
-SlavePort(name, owner), owner(owner), needRetry(false),
+ResponsePort(name, owner), owner(owner), needRetry(false),
 blockedPacket(nullptr)
 { }

@@ -79,7 +79,7 @@

 /**
  * Get a list of the non-overlapping address ranges the owner is
- * responsible for. All slave ports must override this function
+ * responsible for. All response ports must override this function
  * and return a populated list with at least one item.

[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: update port terminology

[Shivani Parekh (Gerrit) via gem5-dev]

Hello Emily Brickey,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/32310

to review the following change.


Change subject: learning-gem5: update port terminology
..

learning-gem5: update port terminology

Change-Id: I0ca705cf93396b5c34a0ac4dce30411c5c866733
---
M src/learning_gem5/part2/SimpleCache.py
M src/learning_gem5/part2/SimpleMemobj.py
M src/learning_gem5/part2/simple_cache.hh
M src/learning_gem5/part2/simple_memobj.hh
4 files changed, 22 insertions(+), 22 deletions(-)



diff --git a/src/learning_gem5/part2/SimpleCache.py  
b/src/learning_gem5/part2/SimpleCache.py

index bd5ebfc..40892b5 100644
--- a/src/learning_gem5/part2/SimpleCache.py
+++ b/src/learning_gem5/part2/SimpleCache.py
@@ -36,7 +36,7 @@
 # Vector port example. Both the instruction and data ports connect to  
this

 # port which is automatically split out into two ports.
 cpu_side = VectorSlavePort("CPU side port, receives requests")
-mem_side = MasterPort("Memory side port, sends requests")
+mem_side = RequestPort("Memory side port, sends requests")

 latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss")

diff --git a/src/learning_gem5/part2/SimpleMemobj.py  
b/src/learning_gem5/part2/SimpleMemobj.py

index aee81c4..b72ebe2 100644
--- a/src/learning_gem5/part2/SimpleMemobj.py
+++ b/src/learning_gem5/part2/SimpleMemobj.py
@@ -32,6 +32,6 @@
 type = 'SimpleMemobj'
 cxx_header = "learning_gem5/part2/simple_memobj.hh"

-inst_port = SlavePort("CPU side port, receives requests")
-data_port = SlavePort("CPU side port, receives requests")
-mem_side = MasterPort("Memory side port, sends requests")
+inst_port = ResponsePort("CPU side port, receives requests")
+data_port = ResponsePort("CPU side port, receives requests")
+mem_side = RequestPort("Memory side port, sends requests")
diff --git a/src/learning_gem5/part2/simple_cache.hh  
b/src/learning_gem5/part2/simple_cache.hh

index dbc128b..4e57c87 100644
--- a/src/learning_gem5/part2/simple_cache.hh
+++ b/src/learning_gem5/part2/simple_cache.hh
@@ -51,7 +51,7 @@
  * Port on the CPU-side that receives requests.
  * Mostly just forwards requests to the cache (owner)
  */
-class CPUSidePort : public SlavePort
+class CPUSidePort : public ResponsePort
 {
   private:
 /// Since this is a vector port, need to know what number this one  
is

@@ -71,7 +71,7 @@
  * Constructor. Just calls the superclass constructor.
  */
 CPUSidePort(const std::string& name, int id, SimpleCache *owner) :
-SlavePort(name, owner), id(id), owner(owner), needRetry(false),
+ResponsePort(name, owner), id(id), owner(owner),  
needRetry(false),

 blockedPacket(nullptr)
 { }

@@ -137,7 +137,7 @@
  * Port on the memory-side that receives responses.
  * Mostly just forwards requests to the cache (owner)
  */
-class MemSidePort : public MasterPort
+class MemSidePort : public RequestPort
 {
   private:
 /// The object that owns this object (SimpleCache)
@@ -151,7 +151,7 @@
  * Constructor. Just calls the superclass constructor.
  */
 MemSidePort(const std::string& name, SimpleCache *owner) :
-MasterPort(name, owner), owner(owner), blockedPacket(nullptr)
+RequestPort(name, owner), owner(owner), blockedPacket(nullptr)
 { }

 /**
diff --git a/src/learning_gem5/part2/simple_memobj.hh  
b/src/learning_gem5/part2/simple_memobj.hh

index b7c57ca..11a4b36 100644
--- a/src/learning_gem5/part2/simple_memobj.hh
+++ b/src/learning_gem5/part2/simple_memobj.hh
@@ -48,7 +48,7 @@
  * Mostly just forwards requests to the owner.
  * Part of a vector of ports. One for each CPU port (e.g., data, inst)
  */
-class CPUSidePort : public SlavePort
+class CPUSidePort : public ResponsePort
 {
   private:
 /// The object that owns this object (SimpleMemobj)
@@ -65,7 +65,7 @@
  * Constructor. Just calls the superclass constructor.
  */
 CPUSidePort(const std::string& name, SimpleMemobj *owner) :
-SlavePort(name, owner), owner(owner), needRetry(false),
+ResponsePort(name, owner), owner(owner), needRetry(false),
 blockedPacket(nullptr)
 { }

@@ -79,7 +79,7 @@

 /**
  * Get a list of the non-overlapping address ranges the owner is
- * responsible for. All slave ports must override this function
+ * responsible for. All response ports must override this function
  * and return a populated list with at least one item.
  *
  * @return a list of ranges responded to
@@ -94,14 +94,14 @@

   protected:
 /**
- * Receive an atomic request packet from the master port.
+ * Receive an