Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46581 )
Change subject: mem,configs,ext,util: Replace ExternalMaster by
ExternalRequestor
......................................................................
mem,configs,ext,util: Replace ExternalMaster by ExternalRequestor
Signed-off-by: Hoa Nguyen <hoangu...@ucdavis.edu>
Change-Id: Icc404e23df1026ec84250520007ce6f4b8f1edd4
---
M configs/common/FSConfig.py
M ext/sst/ExtMaster.cc
M ext/sst/ExtMaster.hh
M ext/sst/README
M ext/sst/gem5.cc
M ext/sst/gem5.hh
R src/mem/ExternalRequestor.py
M src/mem/SConscript
R src/mem/external_requestor.cc
R src/mem/external_requestor.hh
M util/tlm/README
M util/tlm/conf/tlm_master.py
M util/tlm/src/sc_master_port.cc
M util/tlm/src/sc_master_port.hh
M util/tlm/src/sim_control.cc
15 files changed, 62 insertions(+), 60 deletions(-)
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 4c1afce..cc93322 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -299,8 +299,8 @@
if external_memory:
# I/O traffic enters iobus
- self.external_io = ExternalMaster(port_data="external_io",
- port_type=external_memory)
+ self.external_io = ExternalRequestor(port_data="external_io",
+ port_type=external_memory)
self.external_io.port = self.iobus.slave
# Ensure iocache only receives traffic destined for (actual)
memory.
diff --git a/ext/sst/ExtMaster.cc b/ext/sst/ExtMaster.cc
index 3afd6b4..4d6b54f 100644
--- a/ext/sst/ExtMaster.cc
+++ b/ext/sst/ExtMaster.cc
@@ -56,7 +56,7 @@
using namespace SST::gem5;
using namespace SST::MemHierarchy;
-ExtMaster::ExtMaster(gem5Component *g, Output &o, ::ExternalMaster& p,
+ExtMaster::ExtMaster(gem5Component *g, Output &o, ::ExternalRequestor& p,
std::string &n) :
Port(n, p), out(o), port(p), simPhase(CONSTRUCTION),
gem5(g), name(n)
diff --git a/ext/sst/ExtMaster.hh b/ext/sst/ExtMaster.hh
index 04e98e5..ec73993 100644
--- a/ext/sst/ExtMaster.hh
+++ b/ext/sst/ExtMaster.hh
@@ -70,12 +70,12 @@
class gem5Component;
-class ExtMaster : public ExternalMaster::Port {
+class ExtMaster : public ExternalRequestor::Port {
enum Phase { CONSTRUCTION, INIT, RUN };
Output& out;
- const ExternalMaster& port;
+ const ExternalRequestor& port;
Phase simPhase;
gem5Component *const gem5;
@@ -97,7 +97,7 @@
bool recvTimingResp(PacketPtr);
void recvReqRetry();
- ExtMaster(gem5Component*, Output&, ExternalMaster&, std::string&);
+ ExtMaster(gem5Component*, Output&, ExternalRequestor&, std::string&);
void init(unsigned phase);
void setup();
void finish();
@@ -105,7 +105,8 @@
void clock();
// receive Requests from SST bound for a gem5 slave;
- // this module is "external" from gem5's perspective, thus
ExternalMaster.
+ // this module is "external" from gem5's perspective, thus
+ // ExternalRequestor.
void handleEvent(SST::Event*);
protected:
diff --git a/ext/sst/README b/ext/sst/README
index 0dcc45e..834f46b 100644
--- a/ext/sst/README
+++ b/ext/sst/README
@@ -6,7 +6,7 @@
a notion of master and slave. This distinction is important to gem5, so
when connecting a gem5 CPU to an SST cache, an ExternalResponder must be
used,
and similarly when connecting the memory side of SST cache to a gem5 port
-(for memory <-> I/O), an ExternalMaster must be used.
+(for memory <-> I/O), an ExternalRequestor must be used.
The connector handles the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating
@@ -45,7 +45,7 @@
This directory provides:
1. an SST "Component" for gem5;
-2. a class that implements gem5's "ExternalMaster" interface to connect
with
+2. a class that implements gem5's "ExternalRequestor" interface to connect
with
SST "Link"s exchanging "memEvents"
(sst/elements/memHierarchy stuff - caches, memories, etc.)
This lets gem5 receive packets from SST, as in
@@ -60,6 +60,6 @@
v
SST cache hierarchy <-> SST memory
^
- | [ExternalMaster]
+ | [ExternalRequestor]
v
gem5 I/O devices (terminal, disk, etc.)
diff --git a/ext/sst/gem5.cc b/ext/sst/gem5.cc
index b18eadc..e5c2a9f 100644
--- a/ext/sst/gem5.cc
+++ b/ext/sst/gem5.cc
@@ -111,7 +111,7 @@
setDebugFlag(flag);
}
- ExternalMaster::registerHandler("sst", this); // these are idempotent
+ ExternalRequestor::registerHandler("sst", this); // these are
idempotent
ExternalResponder ::registerHandler("sst", this);
// Initialize m5 special signal handling.
@@ -248,9 +248,9 @@
}
}
-ExternalMaster::Port*
+ExternalRequestor::Port*
gem5Component::getExternalPort(const std::string &name,
- ExternalMaster &owner, const std::string &port_data)
+ ExternalRequestor &owner, const std::string &port_data)
{
std::string s(name); // bridges non-& result and &-arg
auto master = new ExtMaster(this, info, owner, s);
diff --git a/ext/sst/gem5.hh b/ext/sst/gem5.hh
index bf8e096..8265fc3 100644
--- a/ext/sst/gem5.hh
+++ b/ext/sst/gem5.hh
@@ -61,7 +61,7 @@
class gem5Component : public SST::Component,
public ExternalResponder::Handler,
- public ExternalMaster::Handler {
+ public ExternalRequestor::Handler {
private:
Output dbg;
@@ -83,8 +83,8 @@
virtual void finish();
bool clockTick(Cycle_t);
- virtual ExternalMaster::Port *getExternalPort(
- const std::string &name, ExternalMaster &owner,
+ virtual ExternalRequestor::Port *getExternalPort(
+ const std::string &name, ExternalRequestor &owner,
const std::string &port_data);
virtual ExternalResponder::Port *getExternalPort(
diff --git a/src/mem/ExternalMaster.py b/src/mem/ExternalRequestor.py
similarity index 94%
rename from src/mem/ExternalMaster.py
rename to src/mem/ExternalRequestor.py
index 6d8b5df..5f83461 100644
--- a/src/mem/ExternalMaster.py
+++ b/src/mem/ExternalRequestor.py
@@ -37,11 +37,11 @@
from m5.proxy import *
from m5.SimObject import SimObject
-class ExternalMaster(SimObject):
- type = 'ExternalMaster'
- cxx_header = "mem/external_master.hh"
+class ExternalRequestor(SimObject):
+ type = 'ExternalRequestor'
+ cxx_header = "mem/external_requestor.hh"
- port = RequestPort("Master port")
+ port = RequestPort("Request port")
port_type = Param.String('stub', 'Registered external port handler'
' to pass this port to in instantiation')
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 3785110..e3b8176 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -50,7 +50,7 @@
SimObject('MemInterface.py')
SimObject('DRAMInterface.py')
SimObject('NVMInterface.py')
-SimObject('ExternalMaster.py')
+SimObject('ExternalRequestor.py')
SimObject('ExternalResponder.py')
SimObject('CfiMemory.py')
SimObject('MemObject.py')
diff --git a/src/mem/external_master.cc b/src/mem/external_requestor.cc
similarity index 87%
rename from src/mem/external_master.cc
rename to src/mem/external_requestor.cc
index 2af175d..caf1fb1 100644
--- a/src/mem/external_master.cc
+++ b/src/mem/external_requestor.cc
@@ -44,10 +44,10 @@
#include "debug/ExternalPort.hh"
#include "sim/system.hh"
-std::map<std::string, ExternalMaster::Handler *>
- ExternalMaster::portHandlers;
+std::map<std::string, ExternalRequestor::Handler *>
+ ExternalRequestor::portHandlers;
-ExternalMaster::ExternalMaster(const ExternalMasterParams ¶ms) :
+ExternalRequestor::ExternalRequestor(const ExternalRequestorParams
¶ms) :
SimObject(params),
externalPort(NULL),
portName(params.name + ".port"),
@@ -57,7 +57,7 @@
{}
Port &
-ExternalMaster::getPort(const std::string &if_name, PortID idx)
+ExternalRequestor::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "port") {
DPRINTF(ExternalPort, "Trying to bind external port: %s %s\n",
@@ -84,17 +84,17 @@
}
void
-ExternalMaster::init()
+ExternalRequestor::init()
{
if (!externalPort) {
- fatal("ExternalMaster %s: externalPort not set!\n", name());
+ fatal("ExternalRequestor %s: externalPort not set!\n", name());
} else if (!externalPort->isConnected()) {
- fatal("ExternalMaster %s is unconnected!\n", name());
+ fatal("ExternalRequestor %s is unconnected!\n", name());
}
}
void
-ExternalMaster::registerHandler(const std::string &handler_name,
+ExternalRequestor::registerHandler(const std::string &handler_name,
Handler *handler)
{
portHandlers[handler_name] = handler;
diff --git a/src/mem/external_master.hh b/src/mem/external_requestor.hh
similarity index 89%
rename from src/mem/external_master.hh
rename to src/mem/external_requestor.hh
index 0ca1936..ede0673 100644
--- a/src/mem/external_master.hh
+++ b/src/mem/external_requestor.hh
@@ -38,7 +38,7 @@
/**
* @file
*
- * ExternalMaster is a memory object representing a binding from
+ * ExternalRequestor is a memory object representing a binding from
* a gem5 responder to a request port in a system external to gem5.
*
* During initialisation, a `handler' for the port type specified in the
@@ -53,25 +53,25 @@
* The external port must provide a gem5 RequestPort interface.
*/
-#ifndef __MEM_EXTERNAL_MASTER_HH__
-#define __MEM_EXTERNAL_MASTER_HH__
+#ifndef __MEM_EXTERNAL_REQUESTOR_HH__
+#define __MEM_EXTERNAL_REQUESTOR_HH__
#include "mem/port.hh"
-#include "params/ExternalMaster.hh"
+#include "params/ExternalRequestor.hh"
#include "sim/sim_object.hh"
-class ExternalMaster : public SimObject
+class ExternalRequestor : public SimObject
{
public:
/** Derive from this class to create an external port interface */
class ExternalPort : public RequestPort
{
protected:
- ExternalMaster &owner;
+ ExternalRequestor &owner;
public:
ExternalPort(const std::string &name_,
- ExternalMaster &owner_) :
+ ExternalRequestor &owner_) :
RequestPort(name_, &owner_), owner(owner_)
{ }
@@ -91,7 +91,7 @@
/** Create or find an external port which can be bound. Returns
* NULL on failure */
virtual ExternalPort *getExternalPort(
- const std::string &name, ExternalMaster &owner,
+ const std::string &name, ExternalRequestor &owner,
const std::string &port_data) = 0;
};
@@ -109,13 +109,13 @@
std::string portData;
/** Registered handlers. Handlers are chosen using the port_type
- * parameter on ExternalMasters. port_types form a global namespace
+ * parameter on ExternalRequestors. port_types form a global
namespace
* across the simulation and so handlers are registered into a global
* structure */
static std::map<std::string, Handler *> portHandlers;
public:
- ExternalMaster(const ExternalMasterParams ¶ms);
+ ExternalRequestor(const ExternalRequestorParams ¶ms);
/** Port interface. Responds only to port "port" */
Port &getPort(const std::string &if_name,
@@ -132,4 +132,4 @@
};
-#endif //__MEM_EXTERNAL_MASTER_HH__
+#endif //__MEM_EXTERNAL_REQUESTOR_HH__
diff --git a/util/tlm/README b/util/tlm/README
index 4639025..f87d303 100644
--- a/util/tlm/README
+++ b/util/tlm/README
@@ -10,14 +10,14 @@
The sources in this directory provide three SystemC modules that manage the
SystemC/gem5 co-simulation: Gem5SimControl, Gem5MasterTransactor, and
-Gem5SlaveTransactor. They also implement gem5's ExternalMaster::Port
interface
-(SCMasterPort) and ExternalResponder::Port interface (SCSlavePort).
+Gem5SlaveTransactor. They also implement gem5's ExternalRequestor::Port
+interface (SCMasterPort) and ExternalResponder::Port interface
(SCSlavePort).
**SCMasterPort** and **Gem5MasterTransactor** together form a TLM-to-gem5
-bridge. SCMasterPort implements gem5's ExternalMaster::Port interface and
forms
-the gem5 end of the bridge. Gem5MasterTransactor is a SystemC module that
-provides a target socket and represents the TLM side of the bridge. All TLM
-requests send to this target socket, are translated to gem5 requests and
+bridge. SCMasterPort implements gem5's ExternalRequestor::Port interface
and
+forms the gem5 end of the bridge. Gem5MasterTransactor is a SystemC module
+that provides a target socket and represents the TLM side of the bridge.
All
+TLM requests send to this target socket, are translated to gem5 requests
and
forwarded to the gem5 world through the SCMasterPort. Then the gem5 world
handles the request and eventually issues a response. When the response
arrives
at the SCMasterPort it gets translated back into a TLM response and
forwarded
diff --git a/util/tlm/conf/tlm_master.py b/util/tlm/conf/tlm_master.py
index fb570d3..ccd36a6 100644
--- a/util/tlm/conf/tlm_master.py
+++ b/util/tlm/conf/tlm_master.py
@@ -56,7 +56,7 @@
voltage_domain = VoltageDomain(voltage = '1V'))
# Create a external TLM port:
-system.tlm = ExternalMaster()
+system.tlm = ExternalRequestor()
system.tlm.port_type = "tlm_master"
system.tlm.port_data = "transactor"
diff --git a/util/tlm/src/sc_master_port.cc b/util/tlm/src/sc_master_port.cc
index f17fc3f..a3cea3a 100644
--- a/util/tlm/src/sc_master_port.cc
+++ b/util/tlm/src/sc_master_port.cc
@@ -33,7 +33,7 @@
#include <sstream>
#include "master_transactor.hh"
-#include "params/ExternalMaster.hh"
+#include "params/ExternalRequestor.hh"
#include "sc_ext.hh"
#include "sc_master_port.hh"
#include "sim/system.hh"
@@ -81,9 +81,9 @@
SCMasterPort::SCMasterPort(const std::string& name_,
const std::string& systemc_name,
- ExternalMaster& owner_,
+ ExternalRequestor& owner_,
Gem5SimControl& simControl)
- : ExternalMaster::ExternalPort(name_, owner_),
+ : ExternalRequestor::ExternalPort(name_, owner_),
peq(this, &SCMasterPort::peq_cb),
waitForRetry(false),
pendingRequest(nullptr),
@@ -93,7 +93,8 @@
transactor(nullptr),
simControl(simControl)
{
- system = dynamic_cast<const
ExternalMasterParams&>(owner_.params()).system;
+ system = \
+ dynamic_cast<const
ExternalRequestorParams&>(owner_.params()).system;
}
void
@@ -404,9 +405,9 @@
"received address range change but ignored it");
}
-ExternalMaster::ExternalPort*
+ExternalRequestor::ExternalPort*
SCMasterPortHandler::getExternalPort(const std::string &name,
- ExternalMaster &owner,
+ ExternalRequestor &owner,
const std::string &port_data)
{
// Create and register a new SystemC master port
diff --git a/util/tlm/src/sc_master_port.hh b/util/tlm/src/sc_master_port.hh
index 93f5194..fe74e0e 100644
--- a/util/tlm/src/sc_master_port.hh
+++ b/util/tlm/src/sc_master_port.hh
@@ -71,7 +71,7 @@
* It is assumed that the mode (atomic/timing) does not change during
* execution.
*/
-class SCMasterPort : public ExternalMaster::ExternalPort
+class SCMasterPort : public ExternalRequestor::ExternalPort
{
private:
struct TlmSenderState : public Packet::SenderState
@@ -120,7 +120,7 @@
public:
SCMasterPort(const std::string& name_,
const std::string& systemc_name,
- ExternalMaster& owner_,
+ ExternalRequestor& owner_,
Gem5SimControl& simControl);
void bindToTransactor(Gem5MasterTransactor* transactor);
@@ -141,7 +141,7 @@
void checkTransaction(tlm::tlm_generic_payload& trans);
};
-class SCMasterPortHandler : public ExternalMaster::Handler
+class SCMasterPortHandler : public ExternalRequestor::Handler
{
private:
Gem5SimControl& control;
@@ -149,8 +149,8 @@
public:
SCMasterPortHandler(Gem5SimControl& control) : control(control) {}
- ExternalMaster::ExternalPort *
- getExternalPort(const std::string &name, ExternalMaster &owner,
+ ExternalRequestor::ExternalPort *
+ getExternalPort(const std::string &name, ExternalRequestor &owner,
const std::string &port_data);
};
diff --git a/util/tlm/src/sim_control.cc b/util/tlm/src/sim_control.cc
index fe6d5bd..a7611f9 100644
--- a/util/tlm/src/sim_control.cc
+++ b/util/tlm/src/sim_control.cc
@@ -77,8 +77,8 @@
// register the systemc slave and master port handler
ExternalResponder::registerHandler("tlm_slave",
new SCSlavePortHandler(*this));
- ExternalMaster::registerHandler("tlm_master",
- new SCMasterPortHandler(*this));
+ ExternalRequestor::registerHandler("tlm_master",
+ new SCMasterPortHandler(*this));
Trace::setDebugLogger(&logger);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46581
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icc404e23df1026ec84250520007ce6f4b8f1edd4
Gerrit-Change-Number: 46581
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen <hoangu...@ucdavis.edu>
Gerrit-MessageType: newchange
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