[gem5-dev] Change in gem5/gem5[develop]: mem: Update port terminology
Shivani Parekh has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32314 )
Change subject: mem: Update port terminology
..
mem: Update port terminology
Change-Id: Ib4fc8cad7139d4971e74930295a69e576f6da3cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32314
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/AddrMapper.py
M src/mem/Bridge.py
M src/mem/CommMonitor.py
M src/mem/ExternalMaster.py
M src/mem/MemChecker.py
M src/mem/MemDelay.py
M src/mem/SerialLink.py
M src/mem/XBar.py
M src/mem/addr_mapper.hh
M src/mem/bridge.cc
M src/mem/bridge.hh
M src/mem/cache/Cache.py
M src/mem/cache/base.hh
M src/mem/coherent_xbar.cc
M src/mem/coherent_xbar.hh
M src/mem/comm_monitor.hh
M src/mem/external_master.hh
M src/mem/hmc_controller.cc
M src/mem/mem_checker_monitor.hh
M src/mem/mem_delay.cc
M src/mem/mem_delay.hh
M src/mem/noncoherent_xbar.cc
M src/mem/noncoherent_xbar.hh
M src/mem/packet_queue.cc
M src/mem/packet_queue.hh
M src/mem/port_proxy.hh
M src/mem/qos/QoSMemSinkCtrl.py
M src/mem/qport.hh
M src/mem/ruby/network/MessageBuffer.py
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/slicc_interface/Controller.py
M src/mem/ruby/system/Sequencer.py
M src/mem/serial_link.cc
M src/mem/serial_link.hh
M src/mem/snoop_filter.cc
M src/mem/snoop_filter.hh
M src/mem/token_port.cc
M src/mem/token_port.hh
M src/mem/xbar.cc
M src/mem/xbar.hh
41 files changed, 155 insertions(+), 153 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/AddrMapper.py b/src/mem/AddrMapper.py
index 1e8dfea..52d7ef8 100644
--- a/src/mem/AddrMapper.py
+++ b/src/mem/AddrMapper.py
@@ -48,8 +48,8 @@
abstract = True
# one port in each direction
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")
# Range address mapper that maps a set of original ranges to a set of
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 95caa0c..a89e7f9 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -42,8 +42,8 @@
class Bridge(ClockedObject):
type = 'Bridge'
cxx_header = "mem/bridge.hh"
-slave = SlavePort('Slave port')
-master = MasterPort('Master port')
+slave = ResponsePort('Slave port')
+master = RequestPort('Master port')
req_size = Param.Unsigned(16, "The number of requests to buffer")
resp_size = Param.Unsigned(16, "The number of responses to buffer")
delay = Param.Latency('0ns', "The latency of this bridge")
diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py
index b1229c7..0fd884d 100644
--- a/src/mem/CommMonitor.py
+++ b/src/mem/CommMonitor.py
@@ -47,8 +47,8 @@
system = Param.System(Parent.any, "System that the monitor belongs
to.")
# one port in each direction
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")
# control the sample period window length of this monitor
sample_period = Param.Clock("1ms", "Sample period for histograms")
diff --git a/src/mem/ExternalMaster.py b/src/mem/ExternalMaster.py
index bcc3836..6d8b5df 100644
--- a/src/mem/ExternalMaster.py
+++ b/src/mem/ExternalMaster.py
@@ -41,7 +41,7 @@
type = 'ExternalMaster'
cxx_header = "mem/external_master.hh"
-port = MasterPort("Master port")
+port = RequestPort("Master port")
port_type = Param.String('stub', 'Registered external port handler'
' to pass this port to in instantiation')
diff --git a/src/mem/MemChecker.py b/src/mem/MemChecker.py
index 0671962..714ea79 100644
--- a/src/mem/MemChecker.py
+++ b/src/mem/MemChecker.py
@@ -46,10 +46,10 @@
cxx_header = "mem/mem_checker_monitor.hh"
# one port in each direction
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
-cpu_side = SlavePort("Alias for slave")
-mem_side = MasterPort("Alias for master")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")
+cpu_side = ResponsePort("Alias for slave")
+mem_side = RequestPort("Alias for master")
warn_only = Param.Bool(False, "Warn about violations only")
memchecker = Param.MemChecker("Instance shared with other monitors")
diff --git a/src/mem/MemDelay.py b/src/mem/MemDelay.py
index fdc0350..7ffb608 100644
--- a/src/mem/MemDelay.py
+++ b/src/mem/MemDelay.py
@@ -41,8 +41,8 @@
cxx_header = 'mem/mem_delay.hh'
abstract = True
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")
class SimpleMemDelay(MemDelay):
type = 'SimpleMemDelay'
[gem5-dev] Change in gem5/gem5[develop]: mem: Update port terminology
Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32314 )
Change subject: mem: Update port terminology
..
mem: Update port terminology
Change-Id: Ib4fc8cad7139d4971e74930295a69e576f6da3cf
---
M src/mem/AddrMapper.py
M src/mem/Bridge.py
M src/mem/CommMonitor.py
M src/mem/ExternalMaster.py
M src/mem/MemChecker.py
M src/mem/MemDelay.py
M src/mem/SerialLink.py
M src/mem/XBar.py
M src/mem/addr_mapper.hh
M src/mem/bridge.cc
M src/mem/bridge.hh
M src/mem/cache/Cache.py
M src/mem/cache/base.hh
M src/mem/coherent_xbar.cc
M src/mem/coherent_xbar.hh
M src/mem/comm_monitor.hh
M src/mem/external_master.hh
M src/mem/hmc_controller.cc
M src/mem/mem_checker_monitor.hh
M src/mem/mem_delay.cc
M src/mem/mem_delay.hh
M src/mem/noncoherent_xbar.cc
M src/mem/noncoherent_xbar.hh
M src/mem/packet_queue.cc
M src/mem/packet_queue.hh
M src/mem/port_proxy.hh
M src/mem/qos/QoSMemSinkCtrl.py
M src/mem/qport.hh
M src/mem/ruby/network/MessageBuffer.py
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/slicc_interface/Controller.py
M src/mem/ruby/system/Sequencer.py
M src/mem/serial_link.cc
M src/mem/serial_link.hh
M src/mem/snoop_filter.cc
M src/mem/snoop_filter.hh
M src/mem/token_port.cc
M src/mem/token_port.hh
M src/mem/xbar.cc
M src/mem/xbar.hh
41 files changed, 155 insertions(+), 153 deletions(-)
diff --git a/src/mem/AddrMapper.py b/src/mem/AddrMapper.py
index 1e8dfea..52d7ef8 100644
--- a/src/mem/AddrMapper.py
+++ b/src/mem/AddrMapper.py
@@ -48,8 +48,8 @@
abstract = True
# one port in each direction
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")
# Range address mapper that maps a set of original ranges to a set of
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 95caa0c..a89e7f9 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -42,8 +42,8 @@
class Bridge(ClockedObject):
type = 'Bridge'
cxx_header = "mem/bridge.hh"
-slave = SlavePort('Slave port')
-master = MasterPort('Master port')
+slave = ResponsePort('Slave port')
+master = RequestPort('Master port')
req_size = Param.Unsigned(16, "The number of requests to buffer")
resp_size = Param.Unsigned(16, "The number of responses to buffer")
delay = Param.Latency('0ns', "The latency of this bridge")
diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py
index b1229c7..0fd884d 100644
--- a/src/mem/CommMonitor.py
+++ b/src/mem/CommMonitor.py
@@ -47,8 +47,8 @@
system = Param.System(Parent.any, "System that the monitor belongs
to.")
# one port in each direction
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")
# control the sample period window length of this monitor
sample_period = Param.Clock("1ms", "Sample period for histograms")
diff --git a/src/mem/ExternalMaster.py b/src/mem/ExternalMaster.py
index bcc3836..6d8b5df 100644
--- a/src/mem/ExternalMaster.py
+++ b/src/mem/ExternalMaster.py
@@ -41,7 +41,7 @@
type = 'ExternalMaster'
cxx_header = "mem/external_master.hh"
-port = MasterPort("Master port")
+port = RequestPort("Master port")
port_type = Param.String('stub', 'Registered external port handler'
' to pass this port to in instantiation')
diff --git a/src/mem/MemChecker.py b/src/mem/MemChecker.py
index 0671962..714ea79 100644
--- a/src/mem/MemChecker.py
+++ b/src/mem/MemChecker.py
@@ -46,10 +46,10 @@
cxx_header = "mem/mem_checker_monitor.hh"
# one port in each direction
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
-cpu_side = SlavePort("Alias for slave")
-mem_side = MasterPort("Alias for master")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")
+cpu_side = ResponsePort("Alias for slave")
+mem_side = RequestPort("Alias for master")
warn_only = Param.Bool(False, "Warn about violations only")
memchecker = Param.MemChecker("Instance shared with other monitors")
diff --git a/src/mem/MemDelay.py b/src/mem/MemDelay.py
index fdc0350..7ffb608 100644
--- a/src/mem/MemDelay.py
+++ b/src/mem/MemDelay.py
@@ -41,8 +41,8 @@
cxx_header = 'mem/mem_delay.hh'
abstract = True
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")
class SimpleMemDelay(MemDelay):
type = 'SimpleMemDelay'
diff --git a/src/mem/SerialLink.py b/src/mem/SerialLink.py
index 254c623..2174bc7 100644
--- a/src/mem/SerialLink.py
+++ b/src/mem/SerialLink.py
@@ -46,8 +46,8 @@
class SerialLink(ClockedObject):
type = 'SerialLink'
cxx_header =
