[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: replace desks, add desc where required

2021-05-27 Thread Hoa Nguyen (Gerrit) via gem5-dev
Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46119 )


Change subject: mem-ruby: replace desks, add desc where required
..

mem-ruby: replace desks, add desc where required

Events in *.sm are required to have "desc" defined.

JIRA: https://gem5.atlassian.net/browse/GEM5-999

Change-Id: I95f59c422bdd264a9e1077b75bf7a0e9f39685aa
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46119
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/chi/CHI-cache.sm
M src/mem/ruby/protocol/chi/CHI-mem.sm
3 files changed, 114 insertions(+), 114 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm

index 03010d5..3b4a801 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -114,7 +114,7 @@
 DMA_WRITE_PARTIAL, desc="DMA Write partial line";
 DMA_ACK,   desc="DMA Ack";
 Data,  desc="Data to directory";
-All_Acks,  desk="All pending acks, unblocks, etc have been  
received";
+All_Acks,  desc="All pending acks, unblocks, etc have been  
received";

   }

   // TYPES
diff --git a/src/mem/ruby/protocol/chi/CHI-cache.sm  
b/src/mem/ruby/protocol/chi/CHI-cache.sm

index 160f674..a0d1888 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache.sm
@@ -206,7 +206,7 @@
   state_declaration(State, default="Cache_State_null") {
 // Stable states

-I, AccessPermission:Invalid,desk="Invalid / not present locally or  
upstream";
+I, AccessPermission:Invalid,desc="Invalid / not present locally or  
upstream";


 // States when block is present in local cache only
 SC, AccessPermission:Read_Only, desc="Shared Clean";
@@ -216,21 +216,21 @@
 UD_T, AccessPermission:Read_Write,  desc="UD with use timeout";

 // Invalid in local cache but present in upstream caches
-RU, AccessPermission:Invalid,   desk="Upstream requester has line in  
UD/UC";
-RSC, AccessPermission:Invalid,  desk="Upstream requester has line in  
SC";
-RSD, AccessPermission:Invalid,  desk="Upstream requester has line in  
SD and maybe SC";
-RUSC, AccessPermission:Invalid, desk="RSC + this node stills has  
exclusive access";
-RUSD, AccessPermission:Invalid, desk="RSD + this node stills has  
exclusive access";
+RU, AccessPermission:Invalid,   desc="Upstream requester has line in  
UD/UC";
+RSC, AccessPermission:Invalid,  desc="Upstream requester has line in  
SC";
+RSD, AccessPermission:Invalid,  desc="Upstream requester has line in  
SD and maybe SC";
+RUSC, AccessPermission:Invalid, desc="RSC + this node stills has  
exclusive access";
+RUSD, AccessPermission:Invalid, desc="RSD + this node stills has  
exclusive access";


 // Both in local and upstream caches. In some cases local maybe stale
-SC_RSC, AccessPermission:Read_Only,desk="SC + RSC";
-SD_RSC, AccessPermission:Read_Only,desk="SD + RSC";
-SD_RSD, AccessPermission:Read_Only,desk="SD + RSD";
-UC_RSC, AccessPermission:Read_Write,   desk="UC + RSC";
-UC_RU, AccessPermission:Invalid,   desk="UC + RU";
-UD_RU, AccessPermission:Invalid,   desk="UD + RU";
-UD_RSD, AccessPermission:Read_Write,   desk="UD + RSD";
-UD_RSC, AccessPermission:Read_Write,   desk="UD + RSC";
+SC_RSC, AccessPermission:Read_Only,desc="SC + RSC";
+SD_RSC, AccessPermission:Read_Only,desc="SD + RSC";
+SD_RSD, AccessPermission:Read_Only,desc="SD + RSD";
+UC_RSC, AccessPermission:Read_Write,   desc="UC + RSC";
+UC_RU, AccessPermission:Invalid,   desc="UC + RU";
+UD_RU, AccessPermission:Invalid,   desc="UD + RU";
+UD_RSD, AccessPermission:Read_Write,   desc="UD + RSD";
+UD_RSC, AccessPermission:Read_Write,   desc="UD + RSC";

 // Generic transient state
 // There is only a transient "BUSY" state. The actions taken at this  
state

@@ -261,90 +261,90 @@

 // Events triggered by sequencer requests or snoops in the rdy queue
 // See CHIRequestType in CHi-msg.sm for descriptions
-Load;
-Store;
-Prefetch;
-ReadShared;
-ReadNotSharedDirty;
-ReadUnique;
-ReadUnique_PoC;
-ReadOnce;
-CleanUnique;
-Evict;
-WriteBackFull;
-WriteEvictFull;
-WriteCleanFull;
-WriteUnique;
-WriteUniquePtl_PoC;
-WriteUniqueFull_PoC;
-WriteUniqueFull_PoC_Alloc;
-SnpCleanInvalid;
-SnpShared;
-SnpSharedFwd;
-SnpNotSharedDirtyFwd;
-SnpUnique;
-SnpUniqueFwd;
-SnpOnce;
-SnpOnceFwd;
-SnpStalled; // A 

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: replace desks, add desc where required

2021-05-27 Thread Hoa Nguyen (Gerrit) via gem5-dev
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46119 )



Change subject: mem-ruby: replace desks, add desc where required
..

mem-ruby: replace desks, add desc where required

Events in *.sm are required to have "desc" defined.

JIRA: https://gem5.atlassian.net/browse/GEM5-999

Change-Id: I95f59c422bdd264a9e1077b75bf7a0e9f39685aa
Signed-off-by: Hoa Nguyen 
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/chi/CHI-cache.sm
M src/mem/ruby/protocol/chi/CHI-mem.sm
3 files changed, 114 insertions(+), 114 deletions(-)



diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm

index 03010d5..3b4a801 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -114,7 +114,7 @@
 DMA_WRITE_PARTIAL, desc="DMA Write partial line";
 DMA_ACK,   desc="DMA Ack";
 Data,  desc="Data to directory";
-All_Acks,  desk="All pending acks, unblocks, etc have been  
received";
+All_Acks,  desc="All pending acks, unblocks, etc have been  
received";

   }

   // TYPES
diff --git a/src/mem/ruby/protocol/chi/CHI-cache.sm  
b/src/mem/ruby/protocol/chi/CHI-cache.sm

index 160f674..a0d1888 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache.sm
@@ -206,7 +206,7 @@
   state_declaration(State, default="Cache_State_null") {
 // Stable states

-I, AccessPermission:Invalid,desk="Invalid / not present locally or  
upstream";
+I, AccessPermission:Invalid,desc="Invalid / not present locally or  
upstream";


 // States when block is present in local cache only
 SC, AccessPermission:Read_Only, desc="Shared Clean";
@@ -216,21 +216,21 @@
 UD_T, AccessPermission:Read_Write,  desc="UD with use timeout";

 // Invalid in local cache but present in upstream caches
-RU, AccessPermission:Invalid,   desk="Upstream requester has line in  
UD/UC";
-RSC, AccessPermission:Invalid,  desk="Upstream requester has line in  
SC";
-RSD, AccessPermission:Invalid,  desk="Upstream requester has line in  
SD and maybe SC";
-RUSC, AccessPermission:Invalid, desk="RSC + this node stills has  
exclusive access";
-RUSD, AccessPermission:Invalid, desk="RSD + this node stills has  
exclusive access";
+RU, AccessPermission:Invalid,   desc="Upstream requester has line in  
UD/UC";
+RSC, AccessPermission:Invalid,  desc="Upstream requester has line in  
SC";
+RSD, AccessPermission:Invalid,  desc="Upstream requester has line in  
SD and maybe SC";
+RUSC, AccessPermission:Invalid, desc="RSC + this node stills has  
exclusive access";
+RUSD, AccessPermission:Invalid, desc="RSD + this node stills has  
exclusive access";


 // Both in local and upstream caches. In some cases local maybe stale
-SC_RSC, AccessPermission:Read_Only,desk="SC + RSC";
-SD_RSC, AccessPermission:Read_Only,desk="SD + RSC";
-SD_RSD, AccessPermission:Read_Only,desk="SD + RSD";
-UC_RSC, AccessPermission:Read_Write,   desk="UC + RSC";
-UC_RU, AccessPermission:Invalid,   desk="UC + RU";
-UD_RU, AccessPermission:Invalid,   desk="UD + RU";
-UD_RSD, AccessPermission:Read_Write,   desk="UD + RSD";
-UD_RSC, AccessPermission:Read_Write,   desk="UD + RSC";
+SC_RSC, AccessPermission:Read_Only,desc="SC + RSC";
+SD_RSC, AccessPermission:Read_Only,desc="SD + RSC";
+SD_RSD, AccessPermission:Read_Only,desc="SD + RSD";
+UC_RSC, AccessPermission:Read_Write,   desc="UC + RSC";
+UC_RU, AccessPermission:Invalid,   desc="UC + RU";
+UD_RU, AccessPermission:Invalid,   desc="UD + RU";
+UD_RSD, AccessPermission:Read_Write,   desc="UD + RSD";
+UD_RSC, AccessPermission:Read_Write,   desc="UD + RSC";

 // Generic transient state
 // There is only a transient "BUSY" state. The actions taken at this  
state

@@ -261,90 +261,90 @@

 // Events triggered by sequencer requests or snoops in the rdy queue
 // See CHIRequestType in CHi-msg.sm for descriptions
-Load;
-Store;
-Prefetch;
-ReadShared;
-ReadNotSharedDirty;
-ReadUnique;
-ReadUnique_PoC;
-ReadOnce;
-CleanUnique;
-Evict;
-WriteBackFull;
-WriteEvictFull;
-WriteCleanFull;
-WriteUnique;
-WriteUniquePtl_PoC;
-WriteUniqueFull_PoC;
-WriteUniqueFull_PoC_Alloc;
-SnpCleanInvalid;
-SnpShared;
-SnpSharedFwd;
-SnpNotSharedDirtyFwd;
-SnpUnique;
-SnpUniqueFwd;
-SnpOnce;
-SnpOnceFwd;
-SnpStalled; // A snoop stall triggered from the inport
+Load,desc="";
+Store,   desc="";
+Prefetch,desc="";
+ReadShared,  desc="";
+ReadNotSharedDirty,  desc="";
+