Mahyar Samani has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51611 )
Change subject: misc: Adding SimpleSingleChannelMemory
......................................................................
misc: Adding SimpleSingleChannelMemory
This change adds SimpleSingleChannelMemory to the components
library.
Change-Id: Id633d207842106a7da8532d3ac64adf022d30d7c
---
M src/python/gem5/components/memory/single_channel.py
1 file changed, 54 insertions(+), 1 deletion(-)
diff --git a/src/python/gem5/components/memory/single_channel.py
b/src/python/gem5/components/memory/single_channel.py
index 11a0b15..1ecdeda 100644
--- a/src/python/gem5/components/memory/single_channel.py
+++ b/src/python/gem5/components/memory/single_channel.py
@@ -31,7 +31,7 @@
from .abstract_memory_system import AbstractMemorySystem
from ...utils.override import overrides
-from m5.objects import AddrRange, DRAMInterface, MemCtrl, Port
+from m5.objects import AddrRange, DRAMInterface, MemCtrl, Port,
SimpleMemory
from m5.util.convert import toMemorySize
from typing import List, Sequence, Tuple, Type, Optional
@@ -99,6 +99,47 @@
self.mem_ctrl.dram.range = ranges[0]
+class SimpleSingleChannelMemory(AbstractMemorySystem):
+ def __init__(
+ self,
+ latency: str,
+ latency_var: str,
+ bandwidth: str,
+ size: Optional[str] = "1GB",
+ ):
+ super().__init__()
+
+ self.module = SimpleMemory(
+ latency=latency, latency_var=latency_var, bandwidth=bandwidth
+ )
+ self._size = toMemorySize(size)
+
+ @overrides(AbstractMemorySystem)
+ def incorporate_memory(self, board: AbstractBoard) -> None:
+ pass
+
+ @overrides(AbstractMemorySystem)
+ def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
+ return [(self.module.range, self.module.port)]
+
+ @overrides(AbstractMemorySystem)
+ def get_memory_controllers(self) -> List[MemCtrl]:
+ return [self.module]
+
+ @overrides(AbstractMemorySystem)
+ def get_size(self) -> int:
+ return self._size
+
+ @overrides(AbstractMemorySystem)
+ def set_memory_range(self, ranges: List[AddrRange]) -> None:
+ if len(ranges) != 1 or ranges[0].size() != self._size:
+ print(ranges[0].size())
+ raise Exception(
+ "Simple single channel memory controller requires a
single "
+ "range which m atches the memory's size."
+ )
+ self.module.range = ranges[0]
+
from .dram_interfaces.ddr3 import DDR3_1600_8x8, DDR3_2133_8x8
from .dram_interfaces.ddr4 import DDR4_2400_8x8
from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id633d207842106a7da8532d3ac64adf022d30d7c
Gerrit-Change-Number: 51611
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani <msam...@ucdavis.edu>
Gerrit-MessageType: newchange
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