[gem5-dev] Change in gem5/gem5[develop]: sparc, configs: Initialize ROMs directly, not with the workload.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27268 )
Change subject: sparc,configs: Initialize ROMs directly, not with the
workload.
..
sparc,configs: Initialize ROMs directly, not with the workload.
This simplifies the SPARC FS workload significantly, and removes
assumptions about what ROMs exist, where they go, etc. It removes
other components from the loop which don't have anything to contribute
as far as setting up the ROMs.
One side effect of this is that there isn't specialized support for
adding PC based events which would fire in the ROMs, but that was never
done and the files that were being used were flat binary blobs with no
symbols in the first place.
This also necessitates building a unified image which goes into the single
8MB ROM that is located at address 0xfff000. That is simply done
with the following commands:
dd if=/dev/zero of=t1000_rom.bin bs=1024 count=8192
dd if=reset_new.bin of=t1000_rom.bin
dd if=q_new.bin of=t1000_rom.bin bs=1024 seek=64
dd if=openboot_new.bin of=t1000_rom.bin bs=1024 seek=512
This results in an 8MB blob which can be loaded verbatim into the ROM.
Alternatively, and with some extra effort, an ELF file could be
constructed which had each of these components as segments, offset to the
right location in the ELF header. That would be slightly more work to set
up,
but wouldn't waste space on regions of the image that are all zeroes.
Change-Id: Id4e08f4e047e7bd36a416c197a36be841eba4a15
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27268
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
---
M configs/common/FSConfig.py
M src/arch/sparc/SparcFsWorkload.py
M src/arch/sparc/fs_workload.cc
M src/arch/sparc/fs_workload.hh
4 files changed, 10 insertions(+), 267 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 41b70d7..376ae1a 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -147,26 +147,20 @@
self.t1000.hvuart.pio_addr + uart_pio_size - 1)
]
-workload = SparcFsWorkload(
-reset_bin=binary('reset_new.bin'),
-hypervisor_bin=binary('q_new.bin'),
-openboot_bin=binary('openboot_new.bin'),
-nvram_bin=binary('nvram1'),
-hypervisor_desc_bin=binary('1up-hv.bin'),
-partition_desc_bin=binary('1up-md.bin'),
-)
+workload = SparcFsWorkload()
# ROM for OBP/Reset/Hypervisor
-self.rom = SimpleMemory(range=AddrRange(workload._rom_base,
size='8MB'))
+self.rom = SimpleMemory(image_file=binary('t1000_rom.bin'),
+range=AddrRange(0xfff000, size='8MB'))
# nvram
-self.nvram = SimpleMemory(
-range=AddrRange(workload._nvram_base, size='8kB'))
+self.nvram = SimpleMemory(image_file=binary('nvram1'),
+range=AddrRange(0x1f1100, size='8kB'))
# hypervisor description
-self.hypervisor_desc = SimpleMemory(
-range=AddrRange(workload._hypervisor_desc_base, size='8kB'))
+self.hypervisor_desc = SimpleMemory(image_file=binary('1up-hv.bin'),
+range=AddrRange(0x1f1208, size='8kB'))
# partition description
-self.partition_desc = SimpleMemory(
-range=AddrRange(workload._partition_desc_base, size='8kB'))
+self.partition_desc = SimpleMemory(image_file=binary('1up-md.bin'),
+range=AddrRange(0x1f1200, size='8kB'))
self.rom.port = self.membus.master
self.nvram.port = self.membus.master
diff --git a/src/arch/sparc/SparcFsWorkload.py
b/src/arch/sparc/SparcFsWorkload.py
index 7f4677e..6244882 100644
--- a/src/arch/sparc/SparcFsWorkload.py
+++ b/src/arch/sparc/SparcFsWorkload.py
@@ -26,7 +26,6 @@
from m5.params import *
-from m5.objects.SimpleMemory import SimpleMemory
from m5.objects.OsKernel import OsKernel
class SparcFsWorkload(OsKernel):
@@ -35,28 +34,3 @@
cxx_class = 'SparcISA::FsWorkload'
load_addr_mask = 0xff
-
-_rom_base = 0xfff000
-_nvram_base = 0x1f1100
-_hypervisor_desc_base = 0x1f1208
-_partition_desc_base = 0x1f1200
-
-reset_addr = Param.Addr(_rom_base, "Address to load ROM at")
-hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base,
- "Address to load hypervisor at")
-openboot_addr = Param.Addr(Addr('512kB') + _rom_base,
- "Address to load openboot at")
-nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram")
-hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base,
-"Address for the hypervisor description")
-partition_desc_addr =
[gem5-dev] Change in gem5/gem5[develop]: sparc, configs: Initialize ROMs directly, not with the workload.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27268 )
Change subject: sparc,configs: Initialize ROMs directly, not with the
workload.
..
sparc,configs: Initialize ROMs directly, not with the workload.
This simplifies the SPARC FS workload significantly, and removes
assumptions about what ROMs exist, where they go, etc. It removes
other components from the loop which don't have anything to contribute
as far as setting up the ROMs.
One side effect of this is that there isn't specialized support for
adding PC based events which would fire in the ROMs, but that was never
done and the files that were being used were flat binary blobs with no
symbols in the first place.
This also necessitates building a unified image which goes into the single
8MB ROM that is located at address 0xfff000. That is simply done
with the following commands:
dd if=/dev/zero of=t1000_rom.bin bs=1024 count=8192
dd if=reset_new.bin of=t1000_rom.bin
dd if=q_new.bin of=t1000_rom.bin bs=1024 seek=64
dd if=openboot_new.bin of=t1000_rom.bin bs=1024 seek=512
This results in an 8MB blob which can be loaded verbatim into the ROM.
Alternatively, and with some extra effort, an ELF file could be
constructed which had each of these components as segments, offset to the
right location in the ELF header. That would be slightly more work to set
up,
but wouldn't waste space on regions of the image that are all zeroes.
Change-Id: Id4e08f4e047e7bd36a416c197a36be841eba4a15
---
M configs/common/FSConfig.py
M src/arch/sparc/SparcFsWorkload.py
M src/arch/sparc/fs_workload.cc
M src/arch/sparc/fs_workload.hh
4 files changed, 10 insertions(+), 267 deletions(-)
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 41b70d7..376ae1a 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -147,26 +147,20 @@
self.t1000.hvuart.pio_addr + uart_pio_size - 1)
]
-workload = SparcFsWorkload(
-reset_bin=binary('reset_new.bin'),
-hypervisor_bin=binary('q_new.bin'),
-openboot_bin=binary('openboot_new.bin'),
-nvram_bin=binary('nvram1'),
-hypervisor_desc_bin=binary('1up-hv.bin'),
-partition_desc_bin=binary('1up-md.bin'),
-)
+workload = SparcFsWorkload()
# ROM for OBP/Reset/Hypervisor
-self.rom = SimpleMemory(range=AddrRange(workload._rom_base,
size='8MB'))
+self.rom = SimpleMemory(image_file=binary('t1000_rom.bin'),
+range=AddrRange(0xfff000, size='8MB'))
# nvram
-self.nvram = SimpleMemory(
-range=AddrRange(workload._nvram_base, size='8kB'))
+self.nvram = SimpleMemory(image_file=binary('nvram1'),
+range=AddrRange(0x1f1100, size='8kB'))
# hypervisor description
-self.hypervisor_desc = SimpleMemory(
-range=AddrRange(workload._hypervisor_desc_base, size='8kB'))
+self.hypervisor_desc = SimpleMemory(image_file=binary('1up-hv.bin'),
+range=AddrRange(0x1f1208, size='8kB'))
# partition description
-self.partition_desc = SimpleMemory(
-range=AddrRange(workload._partition_desc_base, size='8kB'))
+self.partition_desc = SimpleMemory(image_file=binary('1up-md.bin'),
+range=AddrRange(0x1f1200, size='8kB'))
self.rom.port = self.membus.master
self.nvram.port = self.membus.master
diff --git a/src/arch/sparc/SparcFsWorkload.py
b/src/arch/sparc/SparcFsWorkload.py
index 7f4677e..6244882 100644
--- a/src/arch/sparc/SparcFsWorkload.py
+++ b/src/arch/sparc/SparcFsWorkload.py
@@ -26,7 +26,6 @@
from m5.params import *
-from m5.objects.SimpleMemory import SimpleMemory
from m5.objects.OsKernel import OsKernel
class SparcFsWorkload(OsKernel):
@@ -35,28 +34,3 @@
cxx_class = 'SparcISA::FsWorkload'
load_addr_mask = 0xff
-
-_rom_base = 0xfff000
-_nvram_base = 0x1f1100
-_hypervisor_desc_base = 0x1f1208
-_partition_desc_base = 0x1f1200
-
-reset_addr = Param.Addr(_rom_base, "Address to load ROM at")
-hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base,
- "Address to load hypervisor at")
-openboot_addr = Param.Addr(Addr('512kB') + _rom_base,
- "Address to load openboot at")
-nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram")
-hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base,
-"Address for the hypervisor description")
-partition_desc_addr = Param.Addr(_partition_desc_base,
-"Address for the partition description")
-
-reset_bin = Param.String("file that contains the reset code")
-hypervisor_bin = Param.String("file that contains the hypervisor code")
-openboot_bin = Param.String("file that contains the openboot code")
-nvram_bin = Param.String("file that contains the
