[gem5-dev] Change in gem5/gem5[develop]: sparc: Stop using fp_enable_check.

2021-10-13 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48717 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: sparc: Stop using fp_enable_check.
..

sparc: Stop using fp_enable_check.

SPARC and MIPS are the only ISAs using this mechanism. This is a step
towards making them self sufficient and simplifying the ISA parser, it's
interface to the rest of gem5, and it's assumptions about how ISAs are
structured.

Change-Id: Ied85d5012a806321fd717f654d940171da3450af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48717
Tested-by: kokoro 
Reviewed-by: Boris Shingarov 
Maintainer: Gabe Black 
---
M src/arch/sparc/isa/formats/mem/util.isa
M src/arch/sparc/isa/formats/mem/basicmem.isa
M src/arch/sparc/isa/formats/mem/blockmem.isa
M src/arch/sparc/isa/formats/mem/swap.isa
M src/arch/sparc/isa/decoder.isa
M src/arch/sparc/isa/formats/basic.isa
M src/arch/sparc/isa/base.isa
7 files changed, 122 insertions(+), 20 deletions(-)

Approvals:
  Boris Shingarov: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 9adc5ee..8b118f4 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -123,10 +123,9 @@
 /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled
 /// if not.
 static inline Fault
-checkFpEnableFault(ExecContext *xc)
+checkFpEnabled(PSTATE pstate, RegVal fprs)
 {
-PSTATE pstate = xc->readMiscReg(MISCREG_PSTATE);
-if (pstate.pef && xc->readMiscReg(MISCREG_FPRS) & 0x4) {
+if (pstate.pef && fprs & 0x4) {
 return NoFault;
 } else {
 return std::make_shared();
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 9c85cdf..7296c1a 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1258,7 +1258,7 @@
  }}, MEM_SWAP);

 format Trap {
-0x20: Load::ldf({{Frds_uw = Mem_uw;}});
+0x20: Loadf::ldf({{Frds_uw = Mem_uw;}});
 0x21: decode RD {
 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
  if (fault)
@@ -1271,8 +1271,8 @@
 default: FailUnimpl::ldfsrOther();
 }
 0x22: ldqf({{fault = std::make_shared();}});
-0x23: Load::lddf({{Frd_udw = Mem_udw;}});
-0x24: Store::stf({{Mem_uw = Frds_uw;}});
+0x23: Loadf::lddf({{Frd_udw = Mem_udw;}});
+0x24: Storef::stf({{Mem_uw = Frds_uw;}});
 0x25: decode RD {
 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc);
if (fault)
@@ -1285,11 +1285,11 @@
 default: FailUnimpl::stfsrOther();
 }
 0x26: stqf({{fault = std::make_shared();}});
-0x27: Store::stdf({{Mem_udw = Frd_udw;}});
+0x27: Storef::stdf({{Mem_udw = Frd_udw;}});
 0x2D: Nop::prefetch();
-0x30: LoadAlt::ldfa({{Frds_uw = Mem_uw;}});
+0x30: LoadfAlt::ldfa({{Frds_uw = Mem_uw;}});
 0x32: ldqfa({{fault = std::make_shared();}});
-format LoadAlt {
+format LoadfAlt {
 0x33: decode EXT_ASI {
 // ASI_NUCLEUS
 0x04: FailUnimpl::lddfa_n();
@@ -1328,7 +1328,7 @@
 // ASI_SECONDARY_NO_FAULT_LITTLE
 0x8B: FailUnimpl::lddfa_snfl();

-format BlockLoad {
+format BlockLoadf {
 // LDBLOCKF
 // ASI_BLOCK_AS_IF_USER_PRIMARY
 0x16: FailUnimpl::ldblockf_aiup();
@@ -1370,9 +1370,9 @@
 {{fault =  
std::make_shared();}});

 }
 }
-0x34: Store::stfa({{Mem_uw = Frds_uw;}});
+0x34: Storef::stfa({{Mem_uw = Frds_uw;}});
 0x36: stqfa({{fault = std::make_shared();}});
-format StoreAlt {
+format StorefAlt {
 0x37: decode EXT_ASI {
 // ASI_NUCLEUS
 0x04: FailUnimpl::stdfa_n();
@@ -1411,7 +1411,7 @@
 // ASI_SECONDARY_NO_FAULT_LITTLE
 0x8B: FailUnimpl::stdfa_snfl();

-format BlockStore {
+format BlockStoref {
 // STBLOCKF
 // ASI_BLOCK_AS_IF_USER_PRIMARY
 0x16: FailUnimpl::stblockf_aiup();
diff --git a/src/arch/sparc/isa/formats/basic.isa  
b/src/arch/sparc/isa/formats/basic.isa

index e0441b3..0d2346d 100644
--- a/src/arch/sparc/isa/formats

[gem5-dev] Change in gem5/gem5[develop]: sparc: Stop using fp_enable_check.

2021-07-28 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48717 )



Change subject: sparc: Stop using fp_enable_check.
..

sparc: Stop using fp_enable_check.

SPARC and MIPS are the only ISAs using this mechanism. This is a step
towards making them self sufficient and simplifying the ISA parser, it's
interface to the rest of gem5, and it's assumptions about how ISAs are
structured.

Change-Id: Ied85d5012a806321fd717f654d940171da3450af
---
M src/arch/sparc/isa/base.isa
M src/arch/sparc/isa/decoder.isa
M src/arch/sparc/isa/formats/basic.isa
M src/arch/sparc/isa/formats/mem/basicmem.isa
M src/arch/sparc/isa/formats/mem/blockmem.isa
M src/arch/sparc/isa/formats/mem/swap.isa
M src/arch/sparc/isa/formats/mem/util.isa
7 files changed, 104 insertions(+), 20 deletions(-)



diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 9adc5ee..8b118f4 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -123,10 +123,9 @@
 /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled
 /// if not.
 static inline Fault
-checkFpEnableFault(ExecContext *xc)
+checkFpEnabled(PSTATE pstate, RegVal fprs)
 {
-PSTATE pstate = xc->readMiscReg(MISCREG_PSTATE);
-if (pstate.pef && xc->readMiscReg(MISCREG_FPRS) & 0x4) {
+if (pstate.pef && fprs & 0x4) {
 return NoFault;
 } else {
 return std::make_shared();
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 9c85cdf..7296c1a 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1258,7 +1258,7 @@
  }}, MEM_SWAP);

 format Trap {
-0x20: Load::ldf({{Frds_uw = Mem_uw;}});
+0x20: Loadf::ldf({{Frds_uw = Mem_uw;}});
 0x21: decode RD {
 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
  if (fault)
@@ -1271,8 +1271,8 @@
 default: FailUnimpl::ldfsrOther();
 }
 0x22: ldqf({{fault = std::make_shared();}});
-0x23: Load::lddf({{Frd_udw = Mem_udw;}});
-0x24: Store::stf({{Mem_uw = Frds_uw;}});
+0x23: Loadf::lddf({{Frd_udw = Mem_udw;}});
+0x24: Storef::stf({{Mem_uw = Frds_uw;}});
 0x25: decode RD {
 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc);
if (fault)
@@ -1285,11 +1285,11 @@
 default: FailUnimpl::stfsrOther();
 }
 0x26: stqf({{fault = std::make_shared();}});
-0x27: Store::stdf({{Mem_udw = Frd_udw;}});
+0x27: Storef::stdf({{Mem_udw = Frd_udw;}});
 0x2D: Nop::prefetch();
-0x30: LoadAlt::ldfa({{Frds_uw = Mem_uw;}});
+0x30: LoadfAlt::ldfa({{Frds_uw = Mem_uw;}});
 0x32: ldqfa({{fault = std::make_shared();}});
-format LoadAlt {
+format LoadfAlt {
 0x33: decode EXT_ASI {
 // ASI_NUCLEUS
 0x04: FailUnimpl::lddfa_n();
@@ -1328,7 +1328,7 @@
 // ASI_SECONDARY_NO_FAULT_LITTLE
 0x8B: FailUnimpl::lddfa_snfl();

-format BlockLoad {
+format BlockLoadf {
 // LDBLOCKF
 // ASI_BLOCK_AS_IF_USER_PRIMARY
 0x16: FailUnimpl::ldblockf_aiup();
@@ -1370,9 +1370,9 @@
 {{fault =  
std::make_shared();}});

 }
 }
-0x34: Store::stfa({{Mem_uw = Frds_uw;}});
+0x34: Storef::stfa({{Mem_uw = Frds_uw;}});
 0x36: stqfa({{fault = std::make_shared();}});
-format StoreAlt {
+format StorefAlt {
 0x37: decode EXT_ASI {
 // ASI_NUCLEUS
 0x04: FailUnimpl::stdfa_n();
@@ -1411,7 +1411,7 @@
 // ASI_SECONDARY_NO_FAULT_LITTLE
 0x8B: FailUnimpl::stdfa_snfl();

-format BlockStore {
+format BlockStoref {
 // STBLOCKF
 // ASI_BLOCK_AS_IF_USER_PRIMARY
 0x16: FailUnimpl::stblockf_aiup();
diff --git a/src/arch/sparc/isa/formats/basic.isa  
b/src/arch/sparc/isa/formats/basic.isa

index e0441b3..0d2346d 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -104,6 +104,25 @@
 {
 Fault fault = NoFault;

+%(op_decl)s;
+%(op_rd)s;
+%(code)s;
+
+if (fault == NoFault) {
+%(op_wb)s;
+}
+return fault;
+}
+}};
+
+// Basic instruction class execute method template.
+def template FpExecute {{
+Fault
+%(class_name)s::execute(ExecContext *xc,
+Trace::I