[gem5-dev] Change in gem5/gem5[master]: arch: cpu: Track kernel stats using the base ISA agnostic type.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18429 )
Change subject: arch: cpu: Track kernel stats using the base ISA agnostic
type.
..
arch: cpu: Track kernel stats using the base ISA agnostic type.
Then cast to the ISA specific type when necessary. This removes
(mostly) an ISA specific aspect to some of the interfaces. The ISA
specific version of the kernel stats still needs to be constructed and
stored in a few places which means that kernel_stats.hh still needs to
be a switching arch header, for instance.
In the future, I'd like to make the kernel its own object like the
Process objects in SE mode, and then it would be able to instantiate
and maintain its own stats.
Change-Id: I8309d49019124f6bea1482aaea5b5b34e8c97433
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18429
Tested-by: kokoro
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/arch/alpha/ev5.cc
M src/arch/alpha/idle_event.cc
M src/cpu/checker/cpu.cc
M src/cpu/checker/thread_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple/base.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/kern/kernel_stats.hh
M src/sim/pseudo_inst.cc
15 files changed, 53 insertions(+), 46 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index bac8e8d..e3e025e 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -219,6 +219,9 @@
void
ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
{
+auto *stats = dynamic_cast(
+tc->getKernelStats());
+assert(stats || !tc->getKernelStats());
switch (idx) {
case IPR_PALtemp0:
case IPR_PALtemp1:
@@ -267,8 +270,8 @@
case IPR_PALtemp23:
// write entire quad w/ no side-effect
-if (tc->getKernelStats())
-tc->getKernelStats()->context(ipr[idx], val, tc);
+if (stats)
+stats->context(ipr[idx], val, tc);
ipr[idx] = val;
break;
@@ -291,17 +294,17 @@
case IPR_IPLR:
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
-if (tc->getKernelStats())
-tc->getKernelStats()->swpipl(ipr[idx]);
+if (stats)
+stats->swpipl(ipr[idx]);
break;
case IPR_DTB_CM:
if (val & 0x18) {
-if (tc->getKernelStats())
-tc->getKernelStats()->mode(Kernel::user, tc);
+if (stats)
+stats->mode(Kernel::user, tc);
} else {
-if (tc->getKernelStats())
-tc->getKernelStats()->mode(Kernel::kernel, tc);
+if (stats)
+stats->mode(Kernel::kernel, tc);
}
M5_FALLTHROUGH;
@@ -485,6 +488,9 @@
Fault
SimpleThread::hwrei()
{
+auto *stats = dynamic_cast*>(kernelStats);
+assert(stats || !kernelStats);
+
PCState pc = pcState();
if (!(pc.pc() & 0x3))
return std::make_shared();
@@ -494,8 +500,8 @@
CPA::cpa()->swAutoBegin(this, pc.npc());
-if (kernelStats)
-kernelStats->hwrei();
+if (stats)
+stats->hwrei();
// FIXME: XXX check for interrupts? XXX
return NoFault;
@@ -508,8 +514,11 @@
bool
SimpleThread::simPalCheck(int palFunc)
{
-if (kernelStats)
-kernelStats->callpal(palFunc, this);
+auto *stats = dynamic_cast*>(kernelStats);
+assert(stats || !kernelStats);
+
+if (stats)
+stats->callpal(palFunc, this);
switch (palFunc) {
case PAL::halt:
diff --git a/src/arch/alpha/idle_event.cc b/src/arch/alpha/idle_event.cc
index 080dcb2..df8a0c6 100644
--- a/src/arch/alpha/idle_event.cc
+++ b/src/arch/alpha/idle_event.cc
@@ -41,7 +41,10 @@
{
if (tc->getKernelStats()) {
RegVal val = tc->readMiscRegNoEffect(IPR_PALtemp23);
-tc->getKernelStats()->setIdleProcess(val, tc);
+auto *stats = dynamic_cast(
+tc->getKernelStats());
+assert(stats);
+stats->setIdleProcess(val, tc);
}
remove();
}
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index fe1c3d4..7f8eada 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -47,7 +47,6 @@
#include
#include "arch/generic/tlb.hh"
-#include "arch/kernel_stats.hh"
#include "arch/vtophys.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index 26973cd..ed8add6 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -52,10 +52,10 @@
#include "debug/Checker.hh"
class EndQuiesceEvent;
[gem5-dev] Change in gem5/gem5[master]: arch: cpu: Track kernel stats using the base ISA agnostic type.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18429
Change subject: arch: cpu: Track kernel stats using the base ISA agnostic
type.
..
arch: cpu: Track kernel stats using the base ISA agnostic type.
Then cast to the ISA specific type when necessary. This removes
(mostly) an ISA specific aspect to some of the interfaces. The ISA
specific version of the kernel stats still needs to be constructed and
stored in a few places which means that kernel_stats.hh still needs to
be a switching arch header, for instance.
In the future, I'd like to make the kernel its own object like the
Process objects in SE mode, and then it would be able to instantiate
and maintain its own stats.
Change-Id: I8309d49019124f6bea1482aaea5b5b34e8c97433
---
M src/arch/alpha/ev5.cc
M src/arch/alpha/idle_event.cc
M src/cpu/checker/cpu.cc
M src/cpu/checker/thread_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple/base.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/kern/kernel_stats.hh
M src/sim/pseudo_inst.cc
15 files changed, 53 insertions(+), 46 deletions(-)
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index bac8e8d..e3e025e 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -219,6 +219,9 @@
void
ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
{
+auto *stats = dynamic_cast(
+tc->getKernelStats());
+assert(stats || !tc->getKernelStats());
switch (idx) {
case IPR_PALtemp0:
case IPR_PALtemp1:
@@ -267,8 +270,8 @@
case IPR_PALtemp23:
// write entire quad w/ no side-effect
-if (tc->getKernelStats())
-tc->getKernelStats()->context(ipr[idx], val, tc);
+if (stats)
+stats->context(ipr[idx], val, tc);
ipr[idx] = val;
break;
@@ -291,17 +294,17 @@
case IPR_IPLR:
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
-if (tc->getKernelStats())
-tc->getKernelStats()->swpipl(ipr[idx]);
+if (stats)
+stats->swpipl(ipr[idx]);
break;
case IPR_DTB_CM:
if (val & 0x18) {
-if (tc->getKernelStats())
-tc->getKernelStats()->mode(Kernel::user, tc);
+if (stats)
+stats->mode(Kernel::user, tc);
} else {
-if (tc->getKernelStats())
-tc->getKernelStats()->mode(Kernel::kernel, tc);
+if (stats)
+stats->mode(Kernel::kernel, tc);
}
M5_FALLTHROUGH;
@@ -485,6 +488,9 @@
Fault
SimpleThread::hwrei()
{
+auto *stats = dynamic_cast*>(kernelStats);
+assert(stats || !kernelStats);
+
PCState pc = pcState();
if (!(pc.pc() & 0x3))
return std::make_shared();
@@ -494,8 +500,8 @@
CPA::cpa()->swAutoBegin(this, pc.npc());
-if (kernelStats)
-kernelStats->hwrei();
+if (stats)
+stats->hwrei();
// FIXME: XXX check for interrupts? XXX
return NoFault;
@@ -508,8 +514,11 @@
bool
SimpleThread::simPalCheck(int palFunc)
{
-if (kernelStats)
-kernelStats->callpal(palFunc, this);
+auto *stats = dynamic_cast*>(kernelStats);
+assert(stats || !kernelStats);
+
+if (stats)
+stats->callpal(palFunc, this);
switch (palFunc) {
case PAL::halt:
diff --git a/src/arch/alpha/idle_event.cc b/src/arch/alpha/idle_event.cc
index 080dcb2..df8a0c6 100644
--- a/src/arch/alpha/idle_event.cc
+++ b/src/arch/alpha/idle_event.cc
@@ -41,7 +41,10 @@
{
if (tc->getKernelStats()) {
RegVal val = tc->readMiscRegNoEffect(IPR_PALtemp23);
-tc->getKernelStats()->setIdleProcess(val, tc);
+auto *stats = dynamic_cast(
+tc->getKernelStats());
+assert(stats);
+stats->setIdleProcess(val, tc);
}
remove();
}
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index fe1c3d4..7f8eada 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -47,7 +47,6 @@
#include
#include "arch/generic/tlb.hh"
-#include "arch/kernel_stats.hh"
#include "arch/vtophys.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index 26973cd..ed8add6 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -52,10 +52,10 @@
#include "debug/Checker.hh"
class EndQuiesceEvent;
+namespace Kernel {
+class Statistics;
+};
namespace TheISA {
-namespace Kernel {
-class Statistics;
-};
class Decoder;
};
@@ -134,7 +134,7 @@
System *getSystemPtr() override { return actualTC->getSystemPtr(); }
-TheISA::Kernel::Statistics *
