[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Javier Bueno Hedo has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/15215 ) Change subject: mem-cache: Irregular Stream Buffer Prefetcher .. mem-cache: Irregular Stream Buffer Prefetcher Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Reviewed-on: https://gem5-review.googlesource.com/c/15215 Maintainer: Andreas Sandberg Reviewed-by: Daniel Carvalho --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/irregular_stream_buffer.cc A src/mem/cache/prefetch/irregular_stream_buffer.hh 4 files changed, 385 insertions(+), 0 deletions(-) Approvals: Daniel Carvalho: Looks good to me, approved Andreas Sandberg: Looks good to me, approved diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index 7077417..2c31de9 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -266,3 +266,46 @@ DeltaCorrelatingPredictionTables(), "Delta Correlating Prediction Tables object") +class IrregularStreamBufferPrefetcher(QueuedPrefetcher): +type = "IrregularStreamBufferPrefetcher" +cxx_class = "IrregularStreamBufferPrefetcher" +cxx_header = "mem/cache/prefetch/irregular_stream_buffer.hh" + +max_counter_value = Param.Unsigned(3, +"Maximum value of the confidence counter") +chunk_size = Param.Unsigned(256, +"Maximum number of addresses in a temporal stream") +degree = Param.Unsigned(4, "Number of prefetches to generate") +training_unit_assoc = Param.Unsigned(128, +"Associativity of the training unit") +training_unit_entries = Param.MemorySize("128", +"Number of entries of the training unit") +training_unit_indexing_policy = Param.BaseIndexingPolicy( +SetAssociative(entry_size = 1, assoc = Parent.training_unit_assoc, +size = Parent.training_unit_entries), +"Indexing policy of the training unit") +training_unit_replacement_policy = Param.BaseReplacementPolicy(LRURP(), +"Replacement policy of the training unit") + +prefetch_candidates_per_entry = Param.Unsigned(16, +"Number of prefetch candidates stored in a SP-AMC entry") +address_map_cache_assoc = Param.Unsigned(128, +"Associativity of the PS/SP AMCs") +address_map_cache_entries = Param.MemorySize("128", +"Number of entries of the PS/SP AMCs") +ps_address_map_cache_indexing_policy = Param.BaseIndexingPolicy( +SetAssociative(entry_size = 1, +assoc = Parent.address_map_cache_assoc, +size = Parent.address_map_cache_entries), +"Indexing policy of the Physical-to-Structural Address Map Cache") +ps_address_map_cache_replacement_policy = Param.BaseReplacementPolicy( +LRURP(), +"Replacement policy of the Physical-to-Structural Address Map Cache") +sp_address_map_cache_indexing_policy = Param.BaseIndexingPolicy( +SetAssociative(entry_size = 1, +assoc = Parent.address_map_cache_assoc, +size = Parent.address_map_cache_entries), +"Indexing policy of the Structural-to-Physical Address Mao Cache") +sp_address_map_cache_replacement_policy = Param.BaseReplacementPolicy( +LRURP(), +"Replacement policy of the Structural-to-Physical Address Map Cache") diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript index a5d84fd..0a209ff 100644 --- a/src/mem/cache/prefetch/SConscript +++ b/src/mem/cache/prefetch/SConscript @@ -35,6 +35,7 @@ Source('access_map_pattern_matching.cc') Source('base.cc') Source('delta_correlating_prediction_tables.cc') +Source('irregular_stream_buffer.cc') Source('queued.cc') Source('signature_path.cc') Source('signature_path_v2.cc') diff --git a/src/mem/cache/prefetch/irregular_stream_buffer.cc b/src/mem/cache/prefetch/irregular_stream_buffer.cc new file mode 100644 index 000..45aba0b --- /dev/null +++ b/src/mem/cache/prefetch/irregular_stream_buffer.cc @@ -0,0 +1,210 @@ +/** + * Copyright (c) 2018 Metempsy Technology Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Hello Nikos Nikoleris, krishnendra nathella, Dam Sunwoo, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 to look at the new patch set (#7). Change subject: mem-cache: Irregular Stream Buffer Prefetcher .. mem-cache: Irregular Stream Buffer Prefetcher Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/irregular_stream_buffer.cc A src/mem/cache/prefetch/irregular_stream_buffer.hh 4 files changed, 385 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Gerrit-Change-Number: 15215 Gerrit-PatchSet: 7 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Dam Sunwoo Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: krishnendra nathella Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Hello Nikos Nikoleris, krishnendra nathella, Dam Sunwoo, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 to look at the new patch set (#6). Change subject: mem-cache: Irregular Stream Buffer Prefetcher .. mem-cache: Irregular Stream Buffer Prefetcher Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/irregular_stream_buffer.cc A src/mem/cache/prefetch/irregular_stream_buffer.hh 4 files changed, 387 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Gerrit-Change-Number: 15215 Gerrit-PatchSet: 6 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Dam Sunwoo Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: krishnendra nathella Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 to look at the new patch set (#4). Change subject: mem-cache: Irregular Stream Buffer Prefetcher .. mem-cache: Irregular Stream Buffer Prefetcher Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/irregular_stream_buffer.cc A src/mem/cache/prefetch/irregular_stream_buffer.hh 4 files changed, 386 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Gerrit-Change-Number: 15215 Gerrit-PatchSet: 4 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 to look at the new patch set (#3). Change subject: mem-cache: Irregular Stream Buffer Prefetcher .. mem-cache: Irregular Stream Buffer Prefetcher Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/irregular_stream_buffer.cc A src/mem/cache/prefetch/irregular_stream_buffer.hh 4 files changed, 386 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Gerrit-Change-Number: 15215 Gerrit-PatchSet: 3 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Javier Bueno Hedo has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15215 Change subject: mem-cache: Irregular Stream Buffer Prefetcher .. mem-cache: Irregular Stream Buffer Prefetcher Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregar memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/associative_set.hh A src/mem/cache/prefetch/associative_set_impl.hh A src/mem/cache/prefetch/irregular_stream_buffer.cc A src/mem/cache/prefetch/irregular_stream_buffer.hh 6 files changed, 667 insertions(+), 1 deletion(-) diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index df547ed..ec650b5 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -44,6 +44,7 @@ from m5.params import * from m5.proxy import * from ReplacementPolicies import * +from IndexingPolicies import * class HWPProbeEvent(object): def __init__(self, prefetcher, obj, *listOfNames): @@ -139,3 +140,47 @@ cxx_header = "mem/cache/prefetch/tagged.hh" degree = Param.Int(2, "Number of prefetches to generate") + +class IrregularStreamBufferPrefetcher(QueuedPrefetcher): +type = "IrregularStreamBufferPrefetcher" +cxx_class = "IrregularStreamBufferPrefetcher" +cxx_header = "mem/cache/prefetch/irregular_stream_buffer.hh" + +max_counter_value = Param.Unsigned(3, +"Maximum value of the confidence counter") +chunk_size = Param.Unsigned(256, +"Maximum number of addresses in a temporal stream") +degree = Param.Unsigned(4, "Number of prefetches to generate") +training_unit_assoc = Param.Unsigned(128, +"Associativity of the training unit") +training_unit_entries = Param.MemorySize("128", +"Number of entries of the training unit") +training_unit_indexing_policy = Param.BaseIndexingPolicy( +SetAssociative(entry_size = 1, assoc = Parent.training_unit_assoc, +size = Parent.training_unit_entries), +"Indexing policy of the training unit") +training_unit_replacement_policy = Param.BaseReplacementPolicy(LRURP(), +"Replacement policy of the training unit") + +prefetch_candidates_per_entry = Param.Unsigned(16, +"Number of prefetch candidates stored in a SP-AMC entry") +address_map_cache_assoc = Param.Unsigned(128, +"Associativity of the PS/SP AMCs") +address_map_cache_entries = Param.MemorySize("128", +"Number of entries of the PS/SP AMCs") +ps_address_map_cache_indexing_policy = Param.BaseIndexingPolicy( +SetAssociative(entry_size = 1, +assoc = Parent.address_map_cache_assoc, +size = Parent.address_map_cache_entries), +"Indexing policy of the Physical-to-Structural Address Map Cache") +ps_address_map_cache_replacement_policy = Param.BaseReplacementPolicy( +LRURP(), +"Replacement policy of the Physical-to-Structural Address Map Cache") +sp_address_map_cache_indexing_policy = Param.BaseIndexingPolicy( +SetAssociative(entry_size = 1, +assoc = Parent.address_map_cache_assoc, +size = Parent.address_map_cache_entries), +"Indexing policy of the Structural-to-Physical Address Mao Cache") +sp_address_map_cache_replacement_policy = Param.BaseReplacementPolicy( +LRURP(), +"Replacement policy of the Structural-to-Physical Address Map Cache") diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript index 2665d18..00e1dac 100644 --- a/src/mem/cache/prefetch/SConscript +++ b/src/mem/cache/prefetch/SConscript @@ -36,4 +36,4 @@ Source('queued.cc') Source('stride.cc') Source('tagged.cc') - +Source('irregular_stream_buffer.cc') diff --git a/src/mem/cache/prefetch/associative_set.hh b/src/mem/cache/prefetch/associative_set.hh new file mode 100644 index 000..f2314d9 --- /dev/null +++ b/src/mem/cache/prefetch/associative_set.hh @@ -0,0 +1,195 @@ +/** + * Copyright (c) 2018 Metempsy Technology Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of