[gem5-dev] Change in gem5/gem5[master]: systemc: Templatize the gem5/TLM bridge SimObjects.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17234 )
Change subject: systemc: Templatize the gem5/TLM bridge SimObjects.
..
systemc: Templatize the gem5/TLM bridge SimObjects.
The C++ side is templated, and there are python versions for each
(currently two) width of bridge supported.
Change-Id: I4baa9f22d4c87629d45e9e1292eb66c65d25a655
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17234
Reviewed-by: Gabe Black
Maintainer: Gabe Black
---
M src/systemc/tlm_bridge/TlmBridge.py
M src/systemc/tlm_bridge/gem5_to_tlm.cc
M src/systemc/tlm_bridge/gem5_to_tlm.hh
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M src/systemc/tlm_bridge/tlm_to_gem5.hh
5 files changed, 165 insertions(+), 69 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
diff --git a/src/systemc/tlm_bridge/TlmBridge.py
b/src/systemc/tlm_bridge/TlmBridge.py
index d2dff86..dcc5452 100644
--- a/src/systemc/tlm_bridge/TlmBridge.py
+++ b/src/systemc/tlm_bridge/TlmBridge.py
@@ -29,9 +29,10 @@
from m5.params import *
from m5.proxy import *
-class Gem5ToTlmBridge(SystemC_ScModule):
-type = 'Gem5ToTlmBridge'
-cxx_class = 'sc_gem5::Gem5ToTlmBridge'
+class Gem5ToTlmBridgeBase(SystemC_ScModule):
+type = 'Gem5ToTlmBridgeBase'
+abstract = True
+cxx_class = 'sc_gem5::Gem5ToTlmBridgeBase'
cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
system = Param.System(Parent.any, "system")
@@ -41,12 +42,39 @@
addr_ranges = VectorParam.AddrRange([],
'Addresses served by this port\'s TLM side')
-class TlmToGem5Bridge(SystemC_ScModule):
-type = 'TlmToGem5Bridge'
-cxx_class = 'sc_gem5::TlmToGem5Bridge'
+class TlmToGem5BridgeBase(SystemC_ScModule):
+type = 'TlmToGem5BridgeBase'
+abstract = True
+cxx_class = 'sc_gem5::TlmToGem5BridgeBase'
cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
system = Param.System(Parent.any, "system")
gem5 = MasterPort('gem5 master port')
tlm = SlavePort('TLM target socket')
+
+
+class Gem5ToTlmBridge32(Gem5ToTlmBridgeBase):
+type = 'Gem5ToTlmBridge32'
+cxx_template_params = [ 'unsigned int BITWIDTH' ]
+cxx_class = 'sc_gem5::Gem5ToTlmBridge<32>'
+cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
+
+class Gem5ToTlmBridge64(Gem5ToTlmBridgeBase):
+type = 'Gem5ToTlmBridge64'
+cxx_template_params = [ 'unsigned int BITWIDTH' ]
+cxx_class = 'sc_gem5::Gem5ToTlmBridge<64>'
+cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
+
+
+class TlmToGem5Bridge32(TlmToGem5BridgeBase):
+type = 'TlmToGem5Bridge32'
+cxx_template_params = [ 'unsigned int BITWIDTH' ]
+cxx_class = 'sc_gem5::TlmToGem5Bridge<32>'
+cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
+
+class TlmToGem5Bridge64(TlmToGem5BridgeBase):
+type = 'TlmToGem5Bridge64'
+cxx_template_params = [ 'unsigned int BITWIDTH' ]
+cxx_class = 'sc_gem5::TlmToGem5Bridge<64>'
+cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc
b/src/systemc/tlm_bridge/gem5_to_tlm.cc
index 06ed2ab..f78c679 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -63,6 +63,8 @@
#include "systemc/tlm_bridge/gem5_to_tlm.hh"
+#include "params/Gem5ToTlmBridge32.hh"
+#include "params/Gem5ToTlmBridge64.hh"
#include "sim/system.hh"
#include "systemc/tlm_bridge/sc_ext.hh"
#include "systemc/tlm_bridge/sc_mm.hh"
@@ -106,8 +108,10 @@
}
}
+template
void
-Gem5ToTlmBridge::pec(Gem5SystemC::PayloadEvent *pe,
+Gem5ToTlmBridge::pec(
+Gem5SystemC::PayloadEvent> *pe,
tlm::tlm_generic_payload , const tlm::tlm_phase )
{
sc_core::sc_time delay;
@@ -163,8 +167,9 @@
}
// Similar to TLM's blocking transport (LT)
+template
Tick
-Gem5ToTlmBridge::recvAtomic(PacketPtr packet)
+Gem5ToTlmBridge::recvAtomic(PacketPtr packet)
{
panic_if(packet->cacheResponding(),
"Should not see packets where cache is responding");
@@ -205,8 +210,9 @@
return delay.value();
}
+template
void
-Gem5ToTlmBridge::recvFunctionalSnoop(PacketPtr packet)
+Gem5ToTlmBridge::recvFunctionalSnoop(PacketPtr packet)
{
// Snooping should be implemented with tlm_dbg_transport.
SC_REPORT_FATAL("Gem5ToTlmBridge",
@@ -214,8 +220,9 @@
}
// Similar to TLM's non-blocking transport (AT).
+template
bool
-Gem5ToTlmBridge::recvTimingReq(PacketPtr packet)
+Gem5ToTlmBridge::recvTimingReq(PacketPtr packet)
{
panic_if(packet->cacheResponding(),
"Should not see packets where cache is responding");
@@ -309,8 +316,9 @@
return true;
}
+template
bool
-Gem5ToTlmBridge::recvTimingSnoopResp(PacketPtr packet)
+Gem5ToTlmBridge::recvTimingSnoopResp(PacketPtr packet)
{
// Snooping should be implemented with tlm_dbg_transport.
SC_REPORT_FATAL("Gem5ToTlmBridge",
@@
[gem5-dev] Change in gem5/gem5[master]: systemc: Templatize the gem5/TLM bridge SimObjects.
Hello Jason Lowe-Power, Matthias Jung, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17234 to look at the new patch set (#5). Change subject: systemc: Templatize the gem5/TLM bridge SimObjects. .. systemc: Templatize the gem5/TLM bridge SimObjects. The C++ side is templated, and there are python versions for each (currently two) width of bridge supported. Change-Id: I4baa9f22d4c87629d45e9e1292eb66c65d25a655 --- M src/systemc/tlm_bridge/TlmBridge.py M src/systemc/tlm_bridge/gem5_to_tlm.cc M src/systemc/tlm_bridge/gem5_to_tlm.hh M src/systemc/tlm_bridge/tlm_to_gem5.cc M src/systemc/tlm_bridge/tlm_to_gem5.hh 5 files changed, 165 insertions(+), 69 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17234 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I4baa9f22d4c87629d45e9e1292eb66c65d25a655 Gerrit-Change-Number: 17234 Gerrit-PatchSet: 5 Gerrit-Owner: Gabe Black Gerrit-Assignee: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matthias Jung Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: systemc: Templatize the gem5/TLM bridge SimObjects.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17234
Change subject: systemc: Templatize the gem5/TLM bridge SimObjects.
..
systemc: Templatize the gem5/TLM bridge SimObjects.
The C++ side is templated, and there are python versions for each
(currently two) width of bridge supported.
Change-Id: I4baa9f22d4c87629d45e9e1292eb66c65d25a655
---
M src/systemc/tlm_bridge/TlmBridge.py
M src/systemc/tlm_bridge/gem5_to_tlm.cc
M src/systemc/tlm_bridge/gem5_to_tlm.hh
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M src/systemc/tlm_bridge/tlm_to_gem5.hh
5 files changed, 165 insertions(+), 69 deletions(-)
diff --git a/src/systemc/tlm_bridge/TlmBridge.py
b/src/systemc/tlm_bridge/TlmBridge.py
index d2dff86..dcc5452 100644
--- a/src/systemc/tlm_bridge/TlmBridge.py
+++ b/src/systemc/tlm_bridge/TlmBridge.py
@@ -29,9 +29,10 @@
from m5.params import *
from m5.proxy import *
-class Gem5ToTlmBridge(SystemC_ScModule):
-type = 'Gem5ToTlmBridge'
-cxx_class = 'sc_gem5::Gem5ToTlmBridge'
+class Gem5ToTlmBridgeBase(SystemC_ScModule):
+type = 'Gem5ToTlmBridgeBase'
+abstract = True
+cxx_class = 'sc_gem5::Gem5ToTlmBridgeBase'
cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
system = Param.System(Parent.any, "system")
@@ -41,12 +42,39 @@
addr_ranges = VectorParam.AddrRange([],
'Addresses served by this port\'s TLM side')
-class TlmToGem5Bridge(SystemC_ScModule):
-type = 'TlmToGem5Bridge'
-cxx_class = 'sc_gem5::TlmToGem5Bridge'
+class TlmToGem5BridgeBase(SystemC_ScModule):
+type = 'TlmToGem5BridgeBase'
+abstract = True
+cxx_class = 'sc_gem5::TlmToGem5BridgeBase'
cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
system = Param.System(Parent.any, "system")
gem5 = MasterPort('gem5 master port')
tlm = SlavePort('TLM target socket')
+
+
+class Gem5ToTlmBridge32(Gem5ToTlmBridgeBase):
+type = 'Gem5ToTlmBridge32'
+cxx_template_params = [ 'unsigned int BITWIDTH' ]
+cxx_class = 'sc_gem5::Gem5ToTlmBridge<32>'
+cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
+
+class Gem5ToTlmBridge64(Gem5ToTlmBridgeBase):
+type = 'Gem5ToTlmBridge64'
+cxx_template_params = [ 'unsigned int BITWIDTH' ]
+cxx_class = 'sc_gem5::Gem5ToTlmBridge<64>'
+cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
+
+
+class TlmToGem5Bridge32(TlmToGem5BridgeBase):
+type = 'TlmToGem5Bridge32'
+cxx_template_params = [ 'unsigned int BITWIDTH' ]
+cxx_class = 'sc_gem5::TlmToGem5Bridge<32>'
+cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
+
+class TlmToGem5Bridge64(TlmToGem5BridgeBase):
+type = 'TlmToGem5Bridge64'
+cxx_template_params = [ 'unsigned int BITWIDTH' ]
+cxx_class = 'sc_gem5::TlmToGem5Bridge<64>'
+cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc
b/src/systemc/tlm_bridge/gem5_to_tlm.cc
index 4f1f6e4..54cf1a3 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -63,6 +63,8 @@
#include "systemc/tlm_bridge/gem5_to_tlm.hh"
+#include "params/Gem5ToTlmBridge32.hh"
+#include "params/Gem5ToTlmBridge64.hh"
#include "sim/system.hh"
#include "systemc/tlm_bridge/sc_ext.hh"
#include "systemc/tlm_bridge/sc_mm.hh"
@@ -106,8 +108,10 @@
}
}
+template
void
-Gem5ToTlmBridge::pec(Gem5SystemC::PayloadEvent *pe,
+Gem5ToTlmBridge::pec(
+Gem5SystemC::PayloadEvent> *pe,
tlm::tlm_generic_payload , const tlm::tlm_phase )
{
sc_core::sc_time delay;
@@ -163,8 +167,9 @@
}
// Similar to TLM's blocking transport (LT)
+template
Tick
-Gem5ToTlmBridge::recvAtomic(PacketPtr packet)
+Gem5ToTlmBridge::recvAtomic(PacketPtr packet)
{
panic_if(packet->cacheResponding(),
"Should not see packets where cache is responding");
@@ -205,8 +210,9 @@
return delay.value();
}
+template
void
-Gem5ToTlmBridge::recvFunctionalSnoop(PacketPtr packet)
+Gem5ToTlmBridge::recvFunctionalSnoop(PacketPtr packet)
{
// Snooping should be implemented with tlm_dbg_transport.
SC_REPORT_FATAL("Gem5ToTlmBridge",
@@ -214,8 +220,9 @@
}
// Similar to TLM's non-blocking transport (AT).
+template
bool
-Gem5ToTlmBridge::recvTimingReq(PacketPtr packet)
+Gem5ToTlmBridge::recvTimingReq(PacketPtr packet)
{
panic_if(packet->cacheResponding(),
"Should not see packets where cache is responding");
@@ -309,8 +316,9 @@
return true;
}
+template
bool
-Gem5ToTlmBridge::recvTimingSnoopResp(PacketPtr packet)
+Gem5ToTlmBridge::recvTimingSnoopResp(PacketPtr packet)
{
// Snooping should be implemented with tlm_dbg_transport.
SC_REPORT_FATAL("Gem5ToTlmBridge",
@@ -318,14 +326,16 @@
return false;
}
+template
bool
-Gem5ToTlmBridge::tryTiming(PacketPtr packet)
+Gem5ToTlmBridge::tryTiming(PacketPtr packet)
{
panic("tryTiming(PacketPtr) isn't implemented.");
}
