[gem5-dev] Change in gem5/gem5[release-staging-v21-2]: configs: Remove unused WalkCache models

2021-12-16 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54244 )


Change subject: configs: Remove unused WalkCache models
..

configs: Remove unused WalkCache models

Change-Id: Iebda966e72b484ee15cbc7cd62256a950b2a90f1
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54244
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/common/cores/arm/ex5_big.py
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/example/arm/devices.py
5 files changed, 16 insertions(+), 67 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/common/cores/arm/HPI.py  
b/configs/common/cores/arm/HPI.py

index 624c40c..620c01e 100644
--- a/configs/common/cores/arm/HPI.py
+++ b/configs/common/cores/arm/HPI.py
@@ -1332,16 +1332,6 @@
 itb = ArmTLB(entry_type="instruction", size=256)
 dtb = ArmTLB(entry_type="data", size=256)

-class HPI_WalkCache(Cache):
-data_latency = 4
-tag_latency = 4
-response_latency = 4
-mshrs = 6
-tgts_per_mshr = 8
-size = '1kB'
-assoc = 8
-write_buffers = 16
-
 class HPI_BP(TournamentBP):
 localPredictorSize = 64
 localCtrBits = 2
@@ -1442,7 +1432,7 @@

 __all__ = [
 "HPI_BP",
-"HPI_ITB", "HPI_DTB", "HPI_WalkCache",
+"HPI_ITB", "HPI_DTB",
 "HPI_ICache", "HPI_DCache", "HPI_L2",
 "HPI",
 ]
diff --git a/configs/common/cores/arm/O3_ARM_v7a.py  
b/configs/common/cores/arm/O3_ARM_v7a.py

index a402e5f..8cacc65 100644
--- a/configs/common/cores/arm/O3_ARM_v7a.py
+++ b/configs/common/cores/arm/O3_ARM_v7a.py
@@ -169,21 +169,6 @@
 # Consider the L2 a victim cache also for clean lines
 writeback_clean = True

-# TLB Cache
-# Use a cache as a L2 TLB
-class O3_ARM_v7aWalkCache(Cache):
-tag_latency = 4
-data_latency = 4
-response_latency = 4
-mshrs = 6
-tgts_per_mshr = 8
-size = '1kB'
-assoc = 8
-write_buffers = 16
-is_read_only = True
-# Writeback clean lines as well
-writeback_clean = True
-
 # L2 Cache
 class O3_ARM_v7aL2(Cache):
 tag_latency = 12
diff --git a/configs/common/cores/arm/ex5_LITTLE.py  
b/configs/common/cores/arm/ex5_LITTLE.py

index b3f1ad5..bcbaa92 100644
--- a/configs/common/cores/arm/ex5_LITTLE.py
+++ b/configs/common/cores/arm/ex5_LITTLE.py
@@ -112,21 +112,6 @@
 assoc = 4
 write_buffers = 4

-# TLB Cache
-# Use a cache as a L2 TLB
-class WalkCache(Cache):
-tag_latency = 2
-data_latency = 2
-response_latency = 2
-mshrs = 6
-tgts_per_mshr = 8
-size = '1kB'
-assoc = 2
-write_buffers = 16
-is_read_only = True
-# Writeback clean lines as well
-writeback_clean = True
-
 # L2 Cache
 class L2(Cache):
 tag_latency = 9
diff --git a/configs/common/cores/arm/ex5_big.py  
b/configs/common/cores/arm/ex5_big.py

index c734c62..eb5f53f 100644
--- a/configs/common/cores/arm/ex5_big.py
+++ b/configs/common/cores/arm/ex5_big.py
@@ -164,21 +164,6 @@
 assoc = 2
 write_buffers = 16

-# TLB Cache
-# Use a cache as a L2 TLB
-class WalkCache(Cache):
-tag_latency = 4
-data_latency = 4
-response_latency = 4
-mshrs = 6
-tgts_per_mshr = 8
-size = '1kB'
-assoc = 8
-write_buffers = 16
-is_read_only = True
-# Writeback clean lines as well
-writeback_clean = True
-
 # L2 Cache
 class L2(Cache):
 tag_latency = 15
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 5217b08..9122e7c 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -65,17 +65,6 @@
 write_buffers = 16


-class WalkCache(PageTableWalkerCache):
-tag_latency = 4
-data_latency = 4
-response_latency = 4
-mshrs = 6
-tgts_per_mshr = 8
-size = '1kB'
-assoc = 8
-write_buffers = 16
-
-
 class L2(L2Cache):
 tag_latency = 12
 data_latency = 12

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/54244
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-2
Gerrit-Change-Id: Iebda966e72b484ee15cbc7cd62256a950b2a90f1
Gerrit-Change-Number: 54244
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[release-staging-v21-2]: configs: Remove unused WalkCache models

2021-12-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Attention is currently required from: Richard Cooper.
Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/54244

to review the following change.


Change subject: configs: Remove unused WalkCache models
..

configs: Remove unused WalkCache models

Change-Id: Iebda966e72b484ee15cbc7cd62256a950b2a90f1
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M configs/common/cores/arm/ex5_big.py
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/example/arm/devices.py
5 files changed, 12 insertions(+), 67 deletions(-)



diff --git a/configs/common/cores/arm/HPI.py  
b/configs/common/cores/arm/HPI.py

index 624c40c..620c01e 100644
--- a/configs/common/cores/arm/HPI.py
+++ b/configs/common/cores/arm/HPI.py
@@ -1332,16 +1332,6 @@
 itb = ArmTLB(entry_type="instruction", size=256)
 dtb = ArmTLB(entry_type="data", size=256)

-class HPI_WalkCache(Cache):
-data_latency = 4
-tag_latency = 4
-response_latency = 4
-mshrs = 6
-tgts_per_mshr = 8
-size = '1kB'
-assoc = 8
-write_buffers = 16
-
 class HPI_BP(TournamentBP):
 localPredictorSize = 64
 localCtrBits = 2
@@ -1442,7 +1432,7 @@

 __all__ = [
 "HPI_BP",
-"HPI_ITB", "HPI_DTB", "HPI_WalkCache",
+"HPI_ITB", "HPI_DTB",
 "HPI_ICache", "HPI_DCache", "HPI_L2",
 "HPI",
 ]
diff --git a/configs/common/cores/arm/O3_ARM_v7a.py  
b/configs/common/cores/arm/O3_ARM_v7a.py

index a402e5f..8cacc65 100644
--- a/configs/common/cores/arm/O3_ARM_v7a.py
+++ b/configs/common/cores/arm/O3_ARM_v7a.py
@@ -169,21 +169,6 @@
 # Consider the L2 a victim cache also for clean lines
 writeback_clean = True

-# TLB Cache
-# Use a cache as a L2 TLB
-class O3_ARM_v7aWalkCache(Cache):
-tag_latency = 4
-data_latency = 4
-response_latency = 4
-mshrs = 6
-tgts_per_mshr = 8
-size = '1kB'
-assoc = 8
-write_buffers = 16
-is_read_only = True
-# Writeback clean lines as well
-writeback_clean = True
-
 # L2 Cache
 class O3_ARM_v7aL2(Cache):
 tag_latency = 12
diff --git a/configs/common/cores/arm/ex5_LITTLE.py  
b/configs/common/cores/arm/ex5_LITTLE.py

index b3f1ad5..bcbaa92 100644
--- a/configs/common/cores/arm/ex5_LITTLE.py
+++ b/configs/common/cores/arm/ex5_LITTLE.py
@@ -112,21 +112,6 @@
 assoc = 4
 write_buffers = 4

-# TLB Cache
-# Use a cache as a L2 TLB
-class WalkCache(Cache):
-tag_latency = 2
-data_latency = 2
-response_latency = 2
-mshrs = 6
-tgts_per_mshr = 8
-size = '1kB'
-assoc = 2
-write_buffers = 16
-is_read_only = True
-# Writeback clean lines as well
-writeback_clean = True
-
 # L2 Cache
 class L2(Cache):
 tag_latency = 9
diff --git a/configs/common/cores/arm/ex5_big.py  
b/configs/common/cores/arm/ex5_big.py

index c734c62..eb5f53f 100644
--- a/configs/common/cores/arm/ex5_big.py
+++ b/configs/common/cores/arm/ex5_big.py
@@ -164,21 +164,6 @@
 assoc = 2
 write_buffers = 16

-# TLB Cache
-# Use a cache as a L2 TLB
-class WalkCache(Cache):
-tag_latency = 4
-data_latency = 4
-response_latency = 4
-mshrs = 6
-tgts_per_mshr = 8
-size = '1kB'
-assoc = 8
-write_buffers = 16
-is_read_only = True
-# Writeback clean lines as well
-writeback_clean = True
-
 # L2 Cache
 class L2(Cache):
 tag_latency = 15
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 5217b08..9122e7c 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -65,17 +65,6 @@
 write_buffers = 16


-class WalkCache(PageTableWalkerCache):
-tag_latency = 4
-data_latency = 4
-response_latency = 4
-mshrs = 6
-tgts_per_mshr = 8
-size = '1kB'
-assoc = 8
-write_buffers = 16
-
-
 class L2(L2Cache):
 tag_latency = 12
 data_latency = 12

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/54244
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-2
Gerrit-Change-Id: Iebda966e72b484ee15cbc7cd62256a950b2a90f1
Gerrit-Change-Number: 54244
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
Gerrit-MessageType: newchange
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