[gem5-dev] Change in public/gem5[master]: config, mem: l3 cache support
Hello Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/2462 to look at the new patch set (#2). Change subject: config, mem: l3 cache support .. config, mem: l3 cache support Change-Id: I78e3c055d5f312647c4ab4f0c937d6dc4841fb57 Signed-off-by: Pierre-Yves Péneau--- M configs/common/CacheConfig.py M configs/common/Caches.py M configs/common/Options.py M configs/example/fs.py M configs/example/se.py 5 files changed, 44 insertions(+), 11 deletions(-) diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 52659e8..d85a69b 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -60,12 +60,12 @@ print "arm_detailed is unavailable. Did you compile the O3 model?" sys.exit(1) -dcache_class, icache_class, l2_cache_class, walk_cache_class = \ -O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \ -O3_ARM_v7aWalkCache +dcache_class, icache_class, l2_cache_class, l3_cache_class, \ +walk_cache_class = O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, \ +O3_ARM_v7aL2, L3Cache, O3_ARM_v7aWalkCache else: -dcache_class, icache_class, l2_cache_class, walk_cache_class = \ -L1_DCache, L1_ICache, L2Cache, None +dcache_class, icache_class, l2_cache_class, l3_cache_class, \ +walk_cache_class = L1_DCache, L1_ICache, L2Cache, L3Cache, None if buildEnv['TARGET_ISA'] == 'x86': walk_cache_class = PageTableWalkerCache @@ -77,8 +77,21 @@ # minimal so that compute delays do not include memory access latencies. # Configure the compulsory L1 caches for the O3CPU, do not configure # any more caches. -if options.l2cache and options.elastic_trace_en: -fatal("When elastic trace is enabled, do not configure L2 caches.") +if (options.l2cache or options.l3cache) and options.elastic_trace_en: +fatal("When elastic trace is enabled, do not configure L2/L3 caches.") + +if options.l3cache: +# Provide a clock for the L3 and the L2-to-L3 bus here as they +# are not connected using addTwoLevelCacheHierarchy. Use the +# same clock as the CPUs. +system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain, + size=options.l3_size, + assoc=options.l3_assoc) + +system.tol3bus = L2XBar(clk_domain = system.cpu_clk_domain, width=64) +system.l3.cpu_side = system.tol3bus.master +system.l3.mem_side = system.membus.slave + if options.l2cache: # Provide a clock for the L2 and the L1-to-L2 bus here as they @@ -90,7 +103,11 @@ system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain) system.l2.cpu_side = system.tol2bus.master -system.l2.mem_side = system.membus.slave + +if options.l3cache: +system.l2.mem_side = system.tol3bus.slave +else: +system.l2.mem_side = system.membus.slave if options.memchecker: system.memchecker = MemChecker() diff --git a/configs/common/Caches.py b/configs/common/Caches.py index 926a41d..d0ff57e 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -72,6 +72,21 @@ tgts_per_mshr = 12 write_buffers = 8 +class L3Cache(Cache): +assoc = 16 +tag_latency = 30 +data_latency = 30 +response_latency = 30 +mshrs = 30 +tgts_per_mshr = 8 +write_buffers = 10 +size = '16MB' +prefetch_on_access = True +clusivity = 'mostly_excl' +# Simple stride prefetcher +prefetcher = StridePrefetcher(degree=8, latency = 1) +tags = RandomRepl() + class IOCache(Cache): assoc = 8 tag_latency = 50 diff --git a/configs/common/Options.py b/configs/common/Options.py index 9af15ff..49d4af8 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -98,6 +98,7 @@ help="use external port for SystemC TLM cosimulation") parser.add_option("--caches", action="store_true") parser.add_option("--l2cache", action="store_true") +parser.add_option("--l3cache", action="store_true") parser.add_option("--num-dirs", type="int", default=1) parser.add_option("--num-l2caches", type="int", default=1) parser.add_option("--num-l3caches", type="int", default=1) diff --git a/configs/example/fs.py b/configs/example/fs.py index 8102edc..c3aa495 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -183,7 +183,7 @@ cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master else: -if options.caches or options.l2cache: +if options.caches or options.l2cache or options.l3cache: # By default the IOCache runs at the system
[gem5-dev] Change in public/gem5[master]: config, mem: l3 cache support
Pierre-Yves Péneau has uploaded this change for review. ( https://gem5-review.googlesource.com/2462 Change subject: config, mem: l3 cache support .. config, mem: l3 cache support Change-Id: I78e3c055d5f312647c4ab4f0c937d6dc4841fb57 Signed-off-by: Pierre-Yves Péneau--- M configs/common/CacheConfig.py M configs/common/Caches.py M configs/common/O3_ARM_v7a.py M configs/common/Options.py M configs/example/fs.py M configs/example/se.py 6 files changed, 54 insertions(+), 11 deletions(-) diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 52659e8..dd1098d 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -60,12 +60,12 @@ print "arm_detailed is unavailable. Did you compile the O3 model?" sys.exit(1) -dcache_class, icache_class, l2_cache_class, walk_cache_class = \ -O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \ -O3_ARM_v7aWalkCache +dcache_class, icache_class, l2_cache_class, l3_cache_class, \ +walk_cache_class = O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, \ +O3_ARM_v7aL2, O3_ARM_v7aL3, O3_ARM_v7aWalkCache else: -dcache_class, icache_class, l2_cache_class, walk_cache_class = \ -L1_DCache, L1_ICache, L2Cache, None +dcache_class, icache_class, l2_cache_class, l3_cache_class, \ +walk_cache_class = L1_DCache, L1_ICache, L2Cache, L3Cache, None if buildEnv['TARGET_ISA'] == 'x86': walk_cache_class = PageTableWalkerCache @@ -77,8 +77,21 @@ # minimal so that compute delays do not include memory access latencies. # Configure the compulsory L1 caches for the O3CPU, do not configure # any more caches. -if options.l2cache and options.elastic_trace_en: -fatal("When elastic trace is enabled, do not configure L2 caches.") +if (options.l2cache or options.l3cache) and options.elastic_trace_en: +fatal("When elastic trace is enabled, do not configure L2/L3 caches.") + +if options.l3cache: +# Provide a clock for the L3 and the L2-to-L3 bus here as they +# are not connected using addTwoLevelCacheHierarchy. Use the +# same clock as the CPUs. +system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain, + size=options.l3_size, + assoc=options.l3_assoc) + +system.tol3bus = L2XBar(clk_domain = system.cpu_clk_domain, width=64) +system.l3.cpu_side = system.tol3bus.master +system.l3.mem_side = system.membus.slave + if options.l2cache: # Provide a clock for the L2 and the L1-to-L2 bus here as they @@ -90,7 +103,11 @@ system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain) system.l2.cpu_side = system.tol2bus.master -system.l2.mem_side = system.membus.slave + +if options.l3cache: +system.l2.mem_side = system.tol3bus.slave +else: +system.l2.mem_side = system.membus.slave if options.memchecker: system.memchecker = MemChecker() diff --git a/configs/common/Caches.py b/configs/common/Caches.py index 926a41d..86cbc52 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -72,6 +72,15 @@ tgts_per_mshr = 12 write_buffers = 8 +class L3Cache(Cache): +assoc = 16 +tag_latency = 30 +data_latency = 30 +response_latency = 30 +mshrs = 30 +tgts_per_mshr = 8 +write_buffers = 10 + class IOCache(Cache): assoc = 8 tag_latency = 50 diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index f5c2c71..a2a6f94 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -201,3 +201,19 @@ # Simple stride prefetcher prefetcher = StridePrefetcher(degree=8, latency = 1) tags = RandomRepl() + +# L3 Cache +class O3_ARM_v7aL3(Cache): +tag_latency = 30 +data_latency = 30 +response_latency = 30 +mshrs = 30 +tgts_per_mshr = 8 +size = '16MB' +assoc = 16 +write_buffers = 10 +prefetch_on_access = True +clusivity = 'mostly_excl' +# Simple stride prefetcher +prefetcher = StridePrefetcher(degree=8, latency = 1) +tags = RandomRepl() diff --git a/configs/common/Options.py b/configs/common/Options.py index 9af15ff..49d4af8 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -98,6 +98,7 @@ help="use external port for SystemC TLM cosimulation") parser.add_option("--caches", action="store_true") parser.add_option("--l2cache", action="store_true") +parser.add_option("--l3cache", action="store_true") parser.add_option("--num-dirs", type="int", default=1) parser.add_option("--num-l2caches", type="int", default=1)