[gem5-dev] Review Request 2506: x86: Rework opcode parsing to support 3 byte opcodes properly.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2506/ --- Review request for Default. Repository: gem5 Description --- Changeset 10540:18a55f08b76b --- x86: Rework opcode parsing to support 3 byte opcodes properly. Instead of counting the number of opcode bytes in an instruction and recording each byte before the actual opcode, we can represent the path we took to get to the actual opcode byte by using a type code. That has a couple of advantages. First, we can disambiguate the properties of opcodes of the same length which have different properties. Second, it reduces the amount of data stored in an ExtMachInst, making them slightly easier/faster to create and process. This also adds some flexibility as far as how different types of opcodes are handled, which might come in handy if we decide to support VEX or XOP instructions. This change also adds tables to support properly decoding 3 byte opcodes. Before we would fall off the end of some arrays, on top of the ambiguity described above. This change doesn't measureably affect performance on the twolf benchmark. Diffs - src/arch/x86/decoder.hh 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/decoder.cc 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/decoder_tables.cc 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/bitfields.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/decoder.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/locked_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/one_byte_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/three_byte_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/three_byte_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/two_byte_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa_traits.hh 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/types.hh 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/types.cc 1a9e235cab09e37837819876d28fbd2914a47291 Diff: http://reviews.gem5.org/r/2506/diff/ Testing --- Thanks, Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2506: x86: Rework opcode parsing to support 3 byte opcodes properly.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2506/#review5458 --- And found a bug. Update coming. - Gabe Black On Nov. 17, 2014, 6:44 a.m., Gabe Black wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2506/ > --- > > (Updated Nov. 17, 2014, 6:44 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 10540:18a55f08b76b > --- > x86: Rework opcode parsing to support 3 byte opcodes properly. > > Instead of counting the number of opcode bytes in an instruction and recording > each byte before the actual opcode, we can represent the path we took to get > to > the actual opcode byte by using a type code. That has a couple of advantages. > First, we can disambiguate the properties of opcodes of the same length which > have different properties. Second, it reduces the amount of data stored in an > ExtMachInst, making them slightly easier/faster to create and process. This > also adds some flexibility as far as how different types of opcodes are > handled, which might come in handy if we decide to support VEX or XOP > instructions. > > This change also adds tables to support properly decoding 3 byte opcodes. > Before we would fall off the end of some arrays, on top of the ambiguity > described above. > > This change doesn't measureably affect performance on the twolf benchmark. > > > Diffs > - > > src/arch/x86/decoder.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/decoder.cc 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/decoder_tables.cc 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/bitfields.isa 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/decoder.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/locked_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/one_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/three_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/three_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/two_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa_traits.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/types.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/types.cc 1a9e235cab09e37837819876d28fbd2914a47291 > > Diff: http://reviews.gem5.org/r/2506/diff/ > > > Testing > --- > > > Thanks, > > Gabe Black > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2506: x86: Rework opcode parsing to support 3 byte opcodes properly.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2506/ --- (Updated Nov. 17, 2014, 6:55 a.m.) Review request for Default. Repository: gem5 Description (updated) --- Changeset 10540:966f0b63a495 --- x86: Rework opcode parsing to support 3 byte opcodes properly. Instead of counting the number of opcode bytes in an instruction and recording each byte before the actual opcode, we can represent the path we took to get to the actual opcode byte by using a type code. That has a couple of advantages. First, we can disambiguate the properties of opcodes of the same length which have different properties. Second, it reduces the amount of data stored in an ExtMachInst, making them slightly easier/faster to create and process. This also adds some flexibility as far as how different types of opcodes are handled, which might come in handy if we decide to support VEX or XOP instructions. This change also adds tables to support properly decoding 3 byte opcodes. Before we would fall off the end of some arrays, on top of the ambiguity described above. This change doesn't measureably affect performance on the twolf benchmark. Diffs (updated) - src/arch/x86/decoder.hh 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/decoder.cc 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/decoder_tables.cc 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/bitfields.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/decoder.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/locked_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/one_byte_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/three_byte_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/three_byte_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/two_byte_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa_traits.hh 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/types.hh 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/types.cc 1a9e235cab09e37837819876d28fbd2914a47291 Diff: http://reviews.gem5.org/r/2506/diff/ Testing --- Thanks, Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2506: x86: Rework opcode parsing to support 3 byte opcodes properly.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2506/ --- (Updated Nov. 17, 2014, 6:57 a.m.) Review request for Default. Repository: gem5 Description --- Changeset 10540:966f0b63a495 --- x86: Rework opcode parsing to support 3 byte opcodes properly. Instead of counting the number of opcode bytes in an instruction and recording each byte before the actual opcode, we can represent the path we took to get to the actual opcode byte by using a type code. That has a couple of advantages. First, we can disambiguate the properties of opcodes of the same length which have different properties. Second, it reduces the amount of data stored in an ExtMachInst, making them slightly easier/faster to create and process. This also adds some flexibility as far as how different types of opcodes are handled, which might come in handy if we decide to support VEX or XOP instructions. This change also adds tables to support properly decoding 3 byte opcodes. Before we would fall off the end of some arrays, on top of the ambiguity described above. This change doesn't measureably affect performance on the twolf benchmark. Diffs (updated) - src/arch/x86/decoder.hh 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/decoder.cc 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/decoder_tables.cc 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/bitfields.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/decoder.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/locked_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/one_byte_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/three_byte_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/three_byte_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa/decoder/two_byte_opcodes.isa 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/isa_traits.hh 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/types.hh 1a9e235cab09e37837819876d28fbd2914a47291 src/arch/x86/types.cc 1a9e235cab09e37837819876d28fbd2914a47291 Diff: http://reviews.gem5.org/r/2506/diff/ Testing --- Thanks, Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2506: x86: Rework opcode parsing to support 3 byte opcodes properly.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2506/#review5533 --- Ping. - Gabe Black On Nov. 17, 2014, 6:57 a.m., Gabe Black wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2506/ > --- > > (Updated Nov. 17, 2014, 6:57 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 10540:966f0b63a495 > --- > x86: Rework opcode parsing to support 3 byte opcodes properly. > > Instead of counting the number of opcode bytes in an instruction and recording > each byte before the actual opcode, we can represent the path we took to get > to > the actual opcode byte by using a type code. That has a couple of advantages. > First, we can disambiguate the properties of opcodes of the same length which > have different properties. Second, it reduces the amount of data stored in an > ExtMachInst, making them slightly easier/faster to create and process. This > also adds some flexibility as far as how different types of opcodes are > handled, which might come in handy if we decide to support VEX or XOP > instructions. > > This change also adds tables to support properly decoding 3 byte opcodes. > Before we would fall off the end of some arrays, on top of the ambiguity > described above. > > This change doesn't measureably affect performance on the twolf benchmark. > > > Diffs > - > > src/arch/x86/decoder.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/decoder.cc 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/decoder_tables.cc 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/bitfields.isa 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/decoder.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/locked_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/one_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/three_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/three_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/two_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa_traits.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/types.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/types.cc 1a9e235cab09e37837819876d28fbd2914a47291 > > Diff: http://reviews.gem5.org/r/2506/diff/ > > > Testing > --- > > > Thanks, > > Gabe Black > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2506: x86: Rework opcode parsing to support 3 byte opcodes properly.
> On Nov. 24, 2014, 10:06 p.m., Gabe Black wrote: > > Ping. I was traveling all last week and am on vacation all this week, so it might take a bit for me to get to these. - Steve --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2506/#review5533 --- On Nov. 16, 2014, 10:57 p.m., Gabe Black wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2506/ > --- > > (Updated Nov. 16, 2014, 10:57 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 10540:966f0b63a495 > --- > x86: Rework opcode parsing to support 3 byte opcodes properly. > > Instead of counting the number of opcode bytes in an instruction and recording > each byte before the actual opcode, we can represent the path we took to get > to > the actual opcode byte by using a type code. That has a couple of advantages. > First, we can disambiguate the properties of opcodes of the same length which > have different properties. Second, it reduces the amount of data stored in an > ExtMachInst, making them slightly easier/faster to create and process. This > also adds some flexibility as far as how different types of opcodes are > handled, which might come in handy if we decide to support VEX or XOP > instructions. > > This change also adds tables to support properly decoding 3 byte opcodes. > Before we would fall off the end of some arrays, on top of the ambiguity > described above. > > This change doesn't measureably affect performance on the twolf benchmark. > > > Diffs > - > > src/arch/x86/decoder.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/decoder.cc 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/decoder_tables.cc 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/bitfields.isa 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/decoder.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/locked_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/one_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/three_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/three_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/two_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa_traits.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/types.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/types.cc 1a9e235cab09e37837819876d28fbd2914a47291 > > Diff: http://reviews.gem5.org/r/2506/diff/ > > > Testing > --- > > > Thanks, > > Gabe Black > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2506: x86: Rework opcode parsing to support 3 byte opcodes properly.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2506/#review5600 --- Ship it! Looks good, thanks for waiting! - Steve Reinhardt On Nov. 16, 2014, 10:57 p.m., Gabe Black wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2506/ > --- > > (Updated Nov. 16, 2014, 10:57 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 10540:966f0b63a495 > --- > x86: Rework opcode parsing to support 3 byte opcodes properly. > > Instead of counting the number of opcode bytes in an instruction and recording > each byte before the actual opcode, we can represent the path we took to get > to > the actual opcode byte by using a type code. That has a couple of advantages. > First, we can disambiguate the properties of opcodes of the same length which > have different properties. Second, it reduces the amount of data stored in an > ExtMachInst, making them slightly easier/faster to create and process. This > also adds some flexibility as far as how different types of opcodes are > handled, which might come in handy if we decide to support VEX or XOP > instructions. > > This change also adds tables to support properly decoding 3 byte opcodes. > Before we would fall off the end of some arrays, on top of the ambiguity > described above. > > This change doesn't measureably affect performance on the twolf benchmark. > > > Diffs > - > > src/arch/x86/decoder.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/decoder.cc 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/decoder_tables.cc 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/bitfields.isa 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/decoder.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/locked_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/one_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/three_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/three_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/two_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa_traits.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/types.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/types.cc 1a9e235cab09e37837819876d28fbd2914a47291 > > Diff: http://reviews.gem5.org/r/2506/diff/ > > > Testing > --- > > > Thanks, > > Gabe Black > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2506: x86: Rework opcode parsing to support 3 byte opcodes properly.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2506/#review5619 --- Ship it! Ship It! - Nilay Vaish On Nov. 17, 2014, 6:57 a.m., Gabe Black wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2506/ > --- > > (Updated Nov. 17, 2014, 6:57 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 10540:966f0b63a495 > --- > x86: Rework opcode parsing to support 3 byte opcodes properly. > > Instead of counting the number of opcode bytes in an instruction and recording > each byte before the actual opcode, we can represent the path we took to get > to > the actual opcode byte by using a type code. That has a couple of advantages. > First, we can disambiguate the properties of opcodes of the same length which > have different properties. Second, it reduces the amount of data stored in an > ExtMachInst, making them slightly easier/faster to create and process. This > also adds some flexibility as far as how different types of opcodes are > handled, which might come in handy if we decide to support VEX or XOP > instructions. > > This change also adds tables to support properly decoding 3 byte opcodes. > Before we would fall off the end of some arrays, on top of the ambiguity > described above. > > This change doesn't measureably affect performance on the twolf benchmark. > > > Diffs > - > > src/arch/x86/decoder.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/decoder.cc 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/decoder_tables.cc 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/bitfields.isa 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/decoder.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/locked_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/one_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/three_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/three_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa/decoder/two_byte_opcodes.isa > 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/isa_traits.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/types.hh 1a9e235cab09e37837819876d28fbd2914a47291 > src/arch/x86/types.cc 1a9e235cab09e37837819876d28fbd2914a47291 > > Diff: http://reviews.gem5.org/r/2506/diff/ > > > Testing > --- > > > Thanks, > > Gabe Black > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
