changeset 4966471a1ba1 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=4966471a1ba1 description: mem: Update DRAM controller comments
Update comments and add a reference for more information. diffstat: src/mem/dram_ctrl.hh | 34 ++++++++++++++++++---------------- 1 files changed, 18 insertions(+), 16 deletions(-) diffs (45 lines): diff -r e95a0ab1d368 -r 4966471a1ba1 src/mem/dram_ctrl.hh --- a/src/mem/dram_ctrl.hh Tue Aug 26 10:12:45 2014 -0400 +++ b/src/mem/dram_ctrl.hh Tue Aug 26 10:13:03 2014 -0400 @@ -62,23 +62,25 @@ #include "sim/eventq.hh" /** - * The DRAM controller is a basic single-channel memory controller - * aiming to mimic a high-level DRAM controller and the most important - * timing constraints associated with the DRAM. The focus is really on - * modelling the impact on the system rather than the DRAM itself, - * hence the focus is on the controller model and not on the - * memory. By adhering to the correct timing constraints, ultimately - * there is no need for a memory model in addition to the controller - * model. + * The DRAM controller is a single-channel memory controller capturing + * the most important timing constraints associated with a + * contemporary DRAM. For multi-channel memory systems, the controller + * is combined with a crossbar model, with the channel address + * interleaving taking part in the crossbar. * - * As a basic design principle, this controller is not cycle callable, - * but instead uses events to decide when new decisions can be made, - * when resources become available, when things are to be considered - * done, and when to send things back. Through these simple - * principles, we achieve a performant model that is not - * cycle-accurate, but enables us to evaluate the system impact of a - * wide range of memory technologies, and also collect statistics - * about the use of the memory. + * As a basic design principle, this controller + * model is not cycle callable, but instead uses events to: 1) decide + * when new decisions can be made, 2) when resources become available, + * 3) when things are to be considered done, and 4) when to send + * things back. Through these simple principles, the model delivers + * high performance, and lots of flexibility, allowing users to + * evaluate the system impact of a wide range of memory technologies, + * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC. + * + * For more details, please see Hansson et al, "Simulating DRAM + * controllers for future system architecture exploration", + * Proc. ISPASS, 2014. If you use this model as part of your research + * please cite the paper. */ class DRAMCtrl : public AbstractMemory { _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev