Re: [m5-dev] changeset in m5: ARM: Add checkpointing support
> I think this is a good idea. I'm pretty sure you can parse the file with the > python ini package, correct? What would be great is if we could automatically > have a version added to the root object. This seems pretty impossible though, > so perhaps we should create a checkpoint_version parameter on the root > starting with 1. As versions change, it probably shouldn't be too bad to > increment the version number and call a method to go from checkpoint version > to max version by calling every function needed for the translation. I really like this idea. The ConfigParser stuff should do just fine with our files and if there is something wrong in our grammar, we should just fix it. Steve and I have even had several discussions about using something like ConfigParser to build the checkpoint in memory and then spit it out at the end instead of our total hack of generating the checkpoint on the fly. This would make it far simpler to serialize sub-objects. Anyway, maintaining a conversion utility doesn't sound like a huge pain. We need to make some sort of provision for marking changes in the checkpoint functions that are not backward compatible. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Implementation of findTagInSet
Brad, in case you want to have look at the changes that I made so far,
I have attached the patch with this mail.
On Sun, 12 Dec 2010, Nilay Vaish wrote:
Hi Brad,
I have added implicit variables for TBE and Cache entry pointers. These get
inserted in to the doTransition() calls made in Wakeup(). These variables are
forwarded to doTransitionWorker() which passes them on to all the action
functions.
Following is what I think needs to be done next -
1. Currently the implicit TBE and Cache Entry pointers are set to NULL in the
calls to doTransition() function. To set these, we would need to make calls
to a function that returns the pointer if the address is in the cache, NULL
otherwise.
I think we should retain the getEntry functions in the .sm files for in case
of L1 cache both instruction and the data cache needs to be checked. This is
something that I probably would prefer keeping out of SLICC. In fact, we
should add getEntry functions for TBEs where ever required.
These getEntry would now return a pointer instead of a reference. We would
need to add support for return_by_pointer to SLICC. Also, since these
functions would be used inside the Wakeup function, we would need to assume a
common name for them across all protocols, just like getState() function.
2. I still think we would need to change the changePermission function in the
CacheMemory class. Presently it calls findTagInSet() twice. Instead, we would
pass on the CacheEntry whose permissions need to be changed. This would save
one call. We should also put the variable m_locked in the AbstractCacheEntry
(may be make it part of the permission variable) to avoid the second call.
3. In the getState() and setState() functions, we need to specify that the
function assumes that implicit TBE and CacheEntry pointers have been passed
as arguments. How should we do this? I think we would need to push them in to
the symbol table before they can be used in side the function.
Thanks
Nilay
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# HG changeset patch
# Parent 55c51a967be100596c9a4d77514d77289eda1f44
diff -r 55c51a967be1 src/mem/slicc/ast/FuncCallExprAST.py
--- a/src/mem/slicc/ast/FuncCallExprAST.py Thu Dec 09 15:27:12 2010 -0600
+++ b/src/mem/slicc/ast/FuncCallExprAST.py Sat Dec 11 18:20:45 2010 -0600
@@ -115,8 +115,25 @@
code('''
{
Address addr = ${{cvec[1]}};
+''')
+if machine.hasTBEType and machine.hasEntryType:
+code('''
+TransitionResult result = doTransition(${{cvec[0]}},
${machine}_getState(addr), NULL, NULL, addr);
+''')
+elif machine.hasEntryType:
+code('''
+TransitionResult result = doTransition(${{cvec[0]}},
${machine}_getState(addr), NULL, addr);
+''')
+elif machine.hasTBEType:
+code('''
+TransitionResult result = doTransition(${{cvec[0]}},
${machine}_getState(addr), NULL, addr);
+''')
+else:
+code('''
TransitionResult result = doTransition(${{cvec[0]}},
${machine}_getState(addr), addr);
+''')
+code('''
if (result == TransitionResult_Valid) {
counter++;
continue; // Check the first port again
@@ -138,13 +155,13 @@
{
Address addr1 = ${{cvec[1]}};
TransitionResult result1 =
-doTransition(${{cvec[0]}}, ${machine}_getState(addr1), addr1);
+doTransition(${{cvec[0]}}, ${machine}_getState(addr1), addr1, NULL);
if (result1 == TransitionResult_Valid) {
//this second event cannont fail because the first event
// already took effect
Address addr2 = ${{cvec[3]}};
-TransitionResult result2 = doTransition(${{cvec[2]}},
${machine}_getState(addr2), addr2);
+TransitionResult result2 = doTransition(${{cvec[2]}},
${machine}_getState(addr2), addr2, NULL);
// ensure the event suceeded
assert(result2 == TransitionResult_Valid);
diff -r 55c51a967be1 src/mem/slicc/ast/TypeDeclAST.py
--- a/src/mem/slicc/ast/TypeDeclAST.py Thu Dec 09 15:27:12 2010 -0600
+++ b/src/mem/slicc/ast/TypeDeclAST.py Sat Dec 11 18:20:45 2010 -0600
@@ -50,10 +50,15 @@
def generate(self):
ident = str(self.type_ast)
+machine = self.symtab.state_machine
# Make the new type
new_type = Type(self.symtab, ident, self.location, self.pairs,
self.state_machine)
+
+if machine:
+machine.addType(new_type)
+
self.symtab.newSymbol(new_type)
# Add all of the fields of the type to it
diff -r 55c51a967be1 src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py Thu Dec 09 15:27:12 2010 -0600
+++ b/src/mem/slicc/symbols/StateMachine.py Sat Dec 11 18:20:45 2010 -0600
@@ -62,6 +62,8 @@
self.in_ports = []
self.functions = []
self.objects = []
+
Re: [m5-dev] Implementation of findTagInSet
Hi Brad, I have added implicit variables for TBE and Cache entry pointers. These get inserted in to the doTransition() calls made in Wakeup(). These variables are forwarded to doTransitionWorker() which passes them on to all the action functions. Following is what I think needs to be done next - 1. Currently the implicit TBE and Cache Entry pointers are set to NULL in the calls to doTransition() function. To set these, we would need to make calls to a function that returns the pointer if the address is in the cache, NULL otherwise. I think we should retain the getEntry functions in the .sm files for in case of L1 cache both instruction and the data cache needs to be checked. This is something that I probably would prefer keeping out of SLICC. In fact, we should add getEntry functions for TBEs where ever required. These getEntry would now return a pointer instead of a reference. We would need to add support for return_by_pointer to SLICC. Also, since these functions would be used inside the Wakeup function, we would need to assume a common name for them across all protocols, just like getState() function. 2. I still think we would need to change the changePermission function in the CacheMemory class. Presently it calls findTagInSet() twice. Instead, we would pass on the CacheEntry whose permissions need to be changed. This would save one call. We should also put the variable m_locked in the AbstractCacheEntry (may be make it part of the permission variable) to avoid the second call. 3. In the getState() and setState() functions, we need to specify that the function assumes that implicit TBE and CacheEntry pointers have been passed as arguments. How should we do this? I think we would need to push them in to the symbol table before they can be used in side the function. Thanks Nilay On Sat, 11 Dec 2010, Nilay Vaish wrote: Brad We would need to change the lookup functions for TBETable and CacheMemory. Currently the lookup functions assume that the address passed on to the lookup is present. This requires two lookups to the data structures associated with these classes, one for checking whether the address is in the cache, second one for returning a reference to the actual cache entry. Instead of returning a reference, we can return a pointer to the entry. This pointer will be null in case the address is not present in the cache. Nilay On Wed, 8 Dec 2010, Beckmann, Brad wrote: Hi Nilay, Breaking the changes into small portions is a good idea, but we first need to decide exactly what we are doing. So far we've only thrown out some ideas. We have not yet to scope out a complete solution. I think we've settled on passing some sort of reference to the cache and tbe entries, but exactly whether that is by reference variables or pointers isn't clear. My initial preference is to use pointers in the generated code and set the pointers to NULL when a cache and/or tbe entry doesn't exist. However, one thing I really want to strive for is to keep pointer manipulation out of the .sm files. Writing SLICC code is hard enough and we don't want to burden the SLICC programmer with memory management as well. So how about this plan? - Lets remove all the getCacheEntry functions from the slicc files. I believe that almost all of these functions look exactly the same and it is easy enough for SLICC to just generate them instead. - Similarly let get rid of all "isCacheTagPresent" functions as well - Then lets replace all the getCacheEntry calls with an implicit SLICC supported variable called cache_entry and all the TBEs[addr*] calls with an implicit SLICC supported variable called tbe_entry. - Underneath these variables can actually be implemented as local inlined functions that assert whether the entries are valid and then return variables local to the state machine set to the current cache and tbe entry. - The trigger function will implicitly set these variables (pointers underneath) to NULL or valid values, and the only what they can be reset is through explicit functions "set_cache_entry", "reset_cache_entry", "set_tbe_entry", and "reset_tbe_entry". These function would be called by the appropriate actions or possibly be merged with the existing "check_allocate" function. I think that will give us what we want, but I realize I've just proposed changing 100's if not 1000's lines of SLICC code. I hope that these changes are straight forward, but any change like that is never really "straight forward". Let's think it over some more and let me know if you want to discuss this in more detail over-the-phone. Brad ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Cron /z/m5/regression/do-regression --scratch all
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