[m5-dev] changeset in m5: ARM: Fix checkpoint restoration in ARM_SE.

[Ali Saidi]

changeset 70e61aa65759 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=70e61aa65759
description:
ARM: Fix checkpoint restoration in ARM_SE.

diffstat:

 src/arch/arm/linux/process.cc |  4 ++--
 src/arch/arm/linux/process.hh |  2 +-
 src/arch/arm/process.cc   |  4 ++--
 src/arch/arm/process.hh   |  2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diffs (54 lines):

diff -r 1c89a6d235b9 -r 70e61aa65759 src/arch/arm/linux/process.cc
--- a/src/arch/arm/linux/process.cc Sun Apr 10 21:02:28 2011 -0400
+++ b/src/arch/arm/linux/process.cc Sun Apr 10 21:02:28 2011 -0400
@@ -502,9 +502,9 @@
 }
 
 void
-ArmLinuxProcess::startup()
+ArmLinuxProcess::initState()
 {
-ArmLiveProcess::startup();
+ArmLiveProcess::initState();
 pTable->allocate(commPage, PageBytes);
 ThreadContext *tc = system->getThreadContext(contextIds[0]);
 
diff -r 1c89a6d235b9 -r 70e61aa65759 src/arch/arm/linux/process.hh
--- a/src/arch/arm/linux/process.hh Sun Apr 10 21:02:28 2011 -0400
+++ b/src/arch/arm/linux/process.hh Sun Apr 10 21:02:28 2011 -0400
@@ -43,7 +43,7 @@
 
 virtual SyscallDesc* getDesc(int callnum);
 
-void startup();
+void initState();
 
 ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
 void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val);
diff -r 1c89a6d235b9 -r 70e61aa65759 src/arch/arm/process.cc
--- a/src/arch/arm/process.cc   Sun Apr 10 21:02:28 2011 -0400
+++ b/src/arch/arm/process.cc   Sun Apr 10 21:02:28 2011 -0400
@@ -75,9 +75,9 @@
 }
 
 void
-ArmLiveProcess::startup()
+ArmLiveProcess::initState()
 {
-LiveProcess::startup();
+LiveProcess::initState();
 argsInit(MachineBytes, VMPageSize);
 for (int i = 0; i < contextIds.size(); i++) {
 ThreadContext * tc = system->getThreadContext(contextIds[i]);
diff -r 1c89a6d235b9 -r 70e61aa65759 src/arch/arm/process.hh
--- a/src/arch/arm/process.hh   Sun Apr 10 21:02:28 2011 -0400
+++ b/src/arch/arm/process.hh   Sun Apr 10 21:02:28 2011 -0400
@@ -47,7 +47,7 @@
 ArmLiveProcess(LiveProcessParams * params, ObjectFile *objFile,
ObjectFile::Arch _arch);
 
-void startup();
+void initState();
 
   public:
 void argsInit(int intSize, int pageSize);
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[m5-dev] changeset in m5: ARM: Get rid of some comments/todos that no lon...

[Ali Saidi]

changeset 1c89a6d235b9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1c89a6d235b9
description:
ARM: Get rid of some comments/todos that no longer apply.

diffstat:

 src/arch/arm/linux/process.cc |  5 -
 1 files changed, 0 insertions(+), 5 deletions(-)

diffs (22 lines):

diff -r 02cb69e5cfeb -r 1c89a6d235b9 src/arch/arm/linux/process.cc
--- a/src/arch/arm/linux/process.cc Wed Apr 06 14:41:41 2011 -0700
+++ b/src/arch/arm/linux/process.cc Sun Apr 10 21:02:28 2011 -0400
@@ -518,8 +518,6 @@
 swiNeg1, sizeof(swiNeg1));
 }
 
-// We don't have barriers, so just return.
-// @todo Add a barrrier in this code
 uint8_t memory_barrier[] =
 {
 0x5f, 0xf0, 0x7f, 0xf5, // dmb
@@ -528,9 +526,6 @@
 tc->getMemPort()->writeBlob(commPage + 0x0fa0, memory_barrier,
 sizeof(memory_barrier));
 
-// This -should- be atomic, but I don't think all the support that we'd
-// need is implemented. There should also be memory barriers around it.
-// @todo replace this with ldrex/strex and dmb
 uint8_t cmpxchg[] =
 {
 0x9f, 0x3f, 0x92, 0xe1,  // ldrexr3, [r2]
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Re: [m5-dev] Review Request: Core: Add some documentation about the sim clocks.

[Ali Saidi]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/636/#review1106
---



src/sim/core.hh


sounds better to me


- Ali


On 2011-04-10 16:53:18, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/636/
> ---
> 
> (Updated 2011-04-10 16:53:18)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> Core: Add some documentation about the sim clocks.
> 
> 
> Diffs
> -
> 
>   src/sim/core.hh 02cb69e5cfeb 
> 
> Diff: http://reviews.m5sim.org/r/636/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

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Re: [m5-dev] Review Request: Core: Add some documentation about the sim clocks.

[Gabe Black]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/636/#review1105
---



src/sim/core.hh


The way this is worded makes it hard to understand. How about:

These variables equal the number of ticks in the unit of time they're named 
after.


- Gabe


On 2011-04-10 16:53:18, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/636/
> ---
> 
> (Updated 2011-04-10 16:53:18)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> Core: Add some documentation about the sim clocks.
> 
> 
> Diffs
> -
> 
>   src/sim/core.hh 02cb69e5cfeb 
> 
> Diff: http://reviews.m5sim.org/r/636/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

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[m5-dev] Review Request: Core: Add some documentation about the sim clocks.

[Ali Saidi]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/636/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

Core: Add some documentation about the sim clocks.


Diffs
-

  src/sim/core.hh 02cb69e5cfeb 

Diff: http://reviews.m5sim.org/r/636/diff


Testing
---


Thanks,

Ali

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Re: [m5-dev] Review Request: ARM: Make GIC handle IPIs and multiple processors.

[Ali Saidi]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/633/
---

(Updated 2011-04-10 16:52:32.283655)


Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

ARM: Make GIC handle IPIs and multiple processors.


Diffs (updated)
-

  src/dev/arm/gic.hh 02cb69e5cfeb 
  src/dev/arm/gic.cc 02cb69e5cfeb 

Diff: http://reviews.m5sim.org/r/633/diff


Testing
---


Thanks,

Ali

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Re: [m5-dev] Review Request: VNC: Add support for capturing frame buffer to file each time it is changed.

[Ali Saidi]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/631/
---

(Updated 2011-04-10 16:50:13.497059)


Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

VNC: Add support for capturing frame buffer to file each time it is changed.

When a change in the frame buffer from the VNC server is detected, the new
frame is stored out to the m5out/frames_*/ directory.  Specifiy the flag
"--frame-capture" when running configs/example/fs.py to enable this behavior.


Diffs (updated)
-

  configs/example/fs.py 02cb69e5cfeb 
  src/base/bitmap.hh 02cb69e5cfeb 
  src/base/bitmap.cc 02cb69e5cfeb 
  src/base/output.hh 02cb69e5cfeb 
  src/base/output.cc 02cb69e5cfeb 
  src/base/vnc/VncServer.py 02cb69e5cfeb 
  src/base/vnc/convert.hh 02cb69e5cfeb 
  src/base/vnc/convert.cc 02cb69e5cfeb 
  src/base/vnc/vncserver.hh 02cb69e5cfeb 
  src/base/vnc/vncserver.cc 02cb69e5cfeb 

Diff: http://reviews.m5sim.org/r/631/diff


Testing
---


Thanks,

Ali

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[m5-dev] Cron /z/m5/regression/do-regression --scratch all

[Cron Daemon]

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build/ALPHA_FS/tests/fast/quick/80.net

[m5-dev] AccessPermission in AbstractEntry

[Nilay Vaish]

Brad, it seems like the m_Permission variable in AbstractEntry is not 
being used at all. In order to get AccessPermission for a state, the 
state_To_AccessPermission function needs to be called. Then, why have that 
variable? And this would mean that CacheMemory has no idea about the 
access permission, unless we expose the state to Cache Memory class.


Also, as it now stands, it seems one cannot have two different types of 
directory controllers in a system. Is this correct? If yes, then why this 
restriction?


--
Nilay
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