Re: [gem5-dev] Review Request: inorder/dtb: make sure DTB translate correct address

[Korey Sewell]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/743/#review1321
---



src/arch/alpha/tlb.cc


The Request object has a PC in it which is used by the translateInst() 
function. 

Assuming that the PC object is always set correctly in Request, then 
translateData() can also use the Request to get the current PC value rather 
than the last committed state from ThreadContext.


- Korey


On 2011-06-10 22:52:04, Korey Sewell wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/743/
> ---
> 
> (Updated 2011-06-10 22:52:04)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> inorder/dtb: make sure DTB translate correct address
> The DTB expects the correct PC in the ThreadContext
> but how if the memory accesses are speculative? Shouldn't
> we send along the requestor's PC to the translate functions?
> 
> 
> Diffs
> -
> 
>   src/arch/alpha/tlb.cc 77d12d8f7971 
>   src/cpu/inorder/resources/cache_unit.cc 77d12d8f7971 
> 
> Diff: http://reviews.m5sim.org/r/743/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Korey
> 
>

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: inorder/dtb: make sure DTB translate correct address

[Korey Sewell]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/743/
---

(Updated 2011-06-10 22:52:04.462095)


Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

inorder/dtb: make sure DTB translate correct address
The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?


Diffs (updated)
-

  src/arch/alpha/tlb.cc 77d12d8f7971 
  src/cpu/inorder/resources/cache_unit.cc 77d12d8f7971 

Diff: http://reviews.m5sim.org/r/743/diff


Testing
---


Thanks,

Korey

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: cpus/isa: add a != operator for pcstate

[Korey Sewell]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/738/
---

(Updated 2011-06-10 22:38:50.780875)


Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

cpus/isa: add a != operator for pcstate


Diffs (updated)
-

  src/arch/arm/types.hh 77d12d8f7971 
  src/arch/generic/types.hh 77d12d8f7971 

Diff: http://reviews.m5sim.org/r/738/diff


Testing
---


Thanks,

Korey

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: cpus/isa: add a != operator for pcstate

[Korey Sewell]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/738/
---

(Updated 2011-06-10 22:33:40.877518)


Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

cpus/isa: add a != operator for pcstate


Diffs (updated)
-

  src/arch/generic/types.hh 77d12d8f7971 

Diff: http://reviews.m5sim.org/r/738/diff


Testing
---


Thanks,

Korey

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] changeset in gem5: sparc: don't use directcntrl branch flag

[Korey Sewell]

I dont think this was ever working for sparc.

In changeset 77d12d8f7971 (2 days ago?), I added all the sparc control flags
so I'm pretty sure just having the annotation of branch/no branch was new
for sparc.

If you are referring to the o3 early branch resolution, I didnt touch that,
it's just that sparc isnt going to get to use that optimization without the
direct-control branches being annotated correctly. Right now, just the
call/return and indirect-control flags are set through my most recent
changes.

On Fri, Jun 10, 2011 at 11:14 PM, Ali Saidi  wrote:

> This was working at some point.  What happened?
>
> Ali
>
> Sent from my ARM powered device
>
> On Jun 10, 2011, at 9:14 PM, Korey Sewell  wrote:
>
> > changeset 9bb24e6edc35 in /z/repo/gem5
> > details: http://repo.gem5.org/gem5?cmd=changeset;node=9bb24e6edc35
> > description:
> >sparc: don't use directcntrl branch flag
> >this flag is only used for early branch resolution in the O3 model (of
> pc-relative branches)
> >but this isnt cleanly working even when the branch target code is
> added for sparc. For now,
> >we'll ignore this optimization and add a todo in the SPARC ISA for
> future developers
> >
> > diffstat:
> >
> > src/arch/sparc/isa/formats/branch.isa |  5 +++--
> > 1 files changed, 3 insertions(+), 2 deletions(-)
> >
> > diffs (15 lines):
> >
> > diff -r a81aefcef6f9 -r 9bb24e6edc35
> src/arch/sparc/isa/formats/branch.isa
> > --- a/src/arch/sparc/isa/formats/branch.isaFri Jun 10 03:49:23 2011
> -0400
> > +++ b/src/arch/sparc/isa/formats/branch.isaFri Jun 10 22:15:32 2011
> -0400
> > @@ -262,8 +262,9 @@
> > let {{
> > def doBranch(name, Name, base, cond,
> > code, annul_code, fail, annul_fail, opt_flags):
> > -if "IsIndirectControl" not in opt_flags:
> > -   opt_flags += ('IsDirectControl', )
> > +#@todo: add flags and branchTarget() for DirectCntrl branches
> > +#   the o3 model can take advantage of this annotation if
> > +#   done correctly
> >
> > iop = InstObjParams(name, Name, base,
> > {"code": code,
> > ___
> > gem5-dev mailing list
> > gem5-dev@m5sim.org
> > http://m5sim.org/mailman/listinfo/gem5-dev
> >
> ___
> gem5-dev mailing list
> gem5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/gem5-dev
>



-- 
- Korey
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: SLICC: Add a check function for State Machine

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/723/#review1320
---



src/mem/slicc/symbols/StateMachine.py


This print doesn't belong here.  It just makes the output verbose even if 
we don't want it to be.


- Nathan


On 2011-06-01 19:12:30, Nilay Vaish wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/723/
> ---
> 
> (Updated 2011-06-01 19:12:30)
> 
> 
> Review request for Default.
> 
> 
> Summary
> ---
> 
> SLICC: Add a check function for State Machine
> This patch adds a function for State Machines that will check
> whether the provided description in the .sm files includes some
> of the required functions, like getState() and setState().
> 
> 
> Diffs
> -
> 
>   src/mem/slicc/ast/MachineAST.py 681497e0356b 
>   src/mem/slicc/symbols/StateMachine.py 681497e0356b 
> 
> Diff: http://reviews.m5sim.org/r/723/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Nilay
> 
>

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] changeset in gem5: sparc: don't use directcntrl branch flag

[Ali Saidi]

This was working at some point.  What happened?

Ali

Sent from my ARM powered device

On Jun 10, 2011, at 9:14 PM, Korey Sewell  wrote:

> changeset 9bb24e6edc35 in /z/repo/gem5
> details: http://repo.gem5.org/gem5?cmd=changeset;node=9bb24e6edc35
> description:
>sparc: don't use directcntrl branch flag
>this flag is only used for early branch resolution in the O3 model (of 
> pc-relative branches)
>but this isnt cleanly working even when the branch target code is added 
> for sparc. For now,
>we'll ignore this optimization and add a todo in the SPARC ISA for future 
> developers
> 
> diffstat:
> 
> src/arch/sparc/isa/formats/branch.isa |  5 +++--
> 1 files changed, 3 insertions(+), 2 deletions(-)
> 
> diffs (15 lines):
> 
> diff -r a81aefcef6f9 -r 9bb24e6edc35 src/arch/sparc/isa/formats/branch.isa
> --- a/src/arch/sparc/isa/formats/branch.isaFri Jun 10 03:49:23 2011 -0400
> +++ b/src/arch/sparc/isa/formats/branch.isaFri Jun 10 22:15:32 2011 -0400
> @@ -262,8 +262,9 @@
> let {{
> def doBranch(name, Name, base, cond,
> code, annul_code, fail, annul_fail, opt_flags):
> -if "IsIndirectControl" not in opt_flags:
> -   opt_flags += ('IsDirectControl', )
> +#@todo: add flags and branchTarget() for DirectCntrl branches
> +#   the o3 model can take advantage of this annotation if
> +#   done correctly
> 
> iop = InstObjParams(name, Name, base,
> {"code": code,
> ___
> gem5-dev mailing list
> gem5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/gem5-dev
> 
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] changeset in gem5: o3: missing newlines on some dprintfs

[Korey Sewell]

changeset ce8b9a250021 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ce8b9a250021
description:
o3:  missing newlines on some dprintfs

diffstat:

 src/cpu/o3/commit_impl.hh |  4 ++--
 src/cpu/o3/fetch_impl.hh  |  2 +-
 src/cpu/o3/lsq_impl.hh|  6 +++---
 src/cpu/o3/rename_map.cc  |  4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diffs (84 lines):

diff -r 9bb24e6edc35 -r ce8b9a250021 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Fri Jun 10 22:15:32 2011 -0400
+++ b/src/cpu/o3/commit_impl.hh Fri Jun 10 22:15:32 2011 -0400
@@ -118,7 +118,7 @@
 if (policy == "aggressive"){
 commitPolicy = Aggressive;
 
-DPRINTF(Commit,"Commit Policy set to Aggressive.");
+DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
 } else if (policy == "roundrobin"){
 commitPolicy = RoundRobin;
 
@@ -127,7 +127,7 @@
 priority_list.push_back(tid);
 }
 
-DPRINTF(Commit,"Commit Policy set to Round Robin.");
+DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
 } else if (policy == "oldestready"){
 commitPolicy = OldestReady;
 
diff -r 9bb24e6edc35 -r ce8b9a250021 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh  Fri Jun 10 22:15:32 2011 -0400
+++ b/src/cpu/o3/fetch_impl.hh  Fri Jun 10 22:15:32 2011 -0400
@@ -90,7 +90,7 @@
 DefaultFetch::IcachePort::recvFunctional(PacketPtr pkt)
 {
 DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
-"functional call.");
+"functional call.\n");
 }
 
 template
diff -r 9bb24e6edc35 -r ce8b9a250021 src/cpu/o3/lsq_impl.hh
--- a/src/cpu/o3/lsq_impl.hhFri Jun 10 22:15:32 2011 -0400
+++ b/src/cpu/o3/lsq_impl.hhFri Jun 10 22:15:32 2011 -0400
@@ -65,7 +65,7 @@
 void
 LSQ::DcachePort::recvFunctional(PacketPtr pkt)
 {
-DPRINTF(LSQ, "LSQ doesn't update things on a recvFunctional.");
+DPRINTF(LSQ, "LSQ doesn't update things on a recvFunctional.\n");
 }
 
 template 
@@ -151,7 +151,7 @@
 maxSQEntries = SQEntries / numThreads;
 
 DPRINTF(Fetch, "LSQ sharing policy set to Partitioned: "
-"%i entries per LQ | %i entries per SQ",
+"%i entries per LQ | %i entries per SQ\n",
 maxLQEntries,maxSQEntries);
 } else if (policy == "threshold") {
 lsqPolicy = Threshold;
@@ -166,7 +166,7 @@
 maxSQEntries  = params->smtLSQThreshold;
 
 DPRINTF(LSQ, "LSQ sharing policy set to Threshold: "
-"%i entries per LQ | %i entries per SQ",
+"%i entries per LQ | %i entries per SQ\n",
 maxLQEntries,maxSQEntries);
 } else {
 assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic,"
diff -r 9bb24e6edc35 -r ce8b9a250021 src/cpu/o3/rename_map.cc
--- a/src/cpu/o3/rename_map.cc  Fri Jun 10 22:15:32 2011 -0400
+++ b/src/cpu/o3/rename_map.cc  Fri Jun 10 22:15:32 2011 -0400
@@ -88,7 +88,7 @@
 floatRenameMap.resize(numLogicalRegs);
 
 if (bindRegs) {
-DPRINTF(Rename, "Binding registers into rename map %i",id);
+DPRINTF(Rename, "Binding registers into rename map %i\n",id);
 
 // Initialize the entries in the integer rename map to point to the
 // physical registers of the same index
@@ -108,7 +108,7 @@
 floatRenameMap[index].physical_reg = freg_idx++;
 }
 } else {
-DPRINTF(Rename, "Binding registers into rename map %i",id);
+DPRINTF(Rename, "Binding registers into rename map %i\n",id);
 
 PhysRegIndex temp_ireg = ireg_idx;
 
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] changeset in gem5: sparc: update o3 regressions

[Korey Sewell]

changeset ac4da9f8ea80 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ac4da9f8ea80
description:
sparc: update o3 regressions

diffstat:

 tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr|  
   1 -
 tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout|  
  18 +-
 tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt |  
 851 +-
 tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr|  
   1 -
 tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout|  
  48 +-
 tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt |  
3380 +-
 6 files changed, 2145 insertions(+), 2154 deletions(-)

diffs (truncated from 4476 to 300 lines):

diff -r ce8b9a250021 -r ac4da9f8ea80 
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr  Fri Jun 10 
22:15:32 2011 -0400
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr  Fri Jun 10 
22:15:34 2011 -0400
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 hack: be nice to actually delete the event here
diff -r ce8b9a250021 -r ac4da9f8ea80 
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout  Fri Jun 10 
22:15:32 2011 -0400
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout  Fri Jun 10 
22:15:34 2011 -0400
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 21 2011 13:27:10
-M5 started Apr 21 2011 13:28:40
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d 
build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re 
tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
+gem5 compiled Jun 10 2011 22:06:52
+gem5 started Jun 10 2011 22:07:32
+gem5 executing on zooks
+command line: build/SPARC_SE/gem5.opt -d 
build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re 
tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
@@ -22,4 +18,4 @@
 LDTW:  Passed
 STTW:  Passed
 Done
-Exiting @ tick 18633000 because target called exit()
+Exiting @ tick 19016500 because target called exit()
diff -r ce8b9a250021 -r ac4da9f8ea80 
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt   Fri Jun 
10 22:15:32 2011 -0400
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt   Fri Jun 
10 22:15:34 2011 -0400
@@ -1,459 +1,460 @@
 
 -- Begin Simulation Statistics --
-host_inst_rate  79158   # 
Simulator instruction rate (inst/s)
-host_mem_usage 209796   # 
Number of bytes of host memory used
-host_seconds 0.18   # 
Real time elapsed on the host
-host_tick_rate  101982426   # 
Simulator tick rate (ticks/s)
+sim_seconds  0.19   # 
Number of seconds simulated
+sim_ticks19016500   # 
Number of ticks simulated
 sim_freq 1   # 
Frequency of simulated ticks
+host_inst_rate  51742   # 
Simulator instruction rate (inst/s)
+host_tick_rate   68090181   # 
Simulator tick rate (ticks/s)
+host_mem_usage 162768   # 
Number of bytes of host memory used
+host_seconds 0.28   # 
Real time elapsed on the host
 sim_insts   14449   # 
Number of instructions simulated
-sim_seconds  0.19   # 
Number of seconds simulated
-sim_ticks18633000   # 
Number of ticks simulated
+system.cpu.workload.num_syscalls   18   # 
Number of system calls
+system.cpu.numCycles38034   # 
number of cpu cycles simulated
+system.cpu.numWorkItemsStarted  0   # 
number of work items this cpu started
+system.cpu.n

[gem5-dev] changeset in gem5: sparc: don't use directcntrl branch flag

[Korey Sewell]

changeset 9bb24e6edc35 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9bb24e6edc35
description:
sparc: don't use directcntrl branch flag
this flag is only used for early branch resolution in the O3 model (of 
pc-relative branches)
but this isnt cleanly working even when the branch target code is added 
for sparc. For now,
we'll ignore this optimization and add a todo in the SPARC ISA for 
future developers

diffstat:

 src/arch/sparc/isa/formats/branch.isa |  5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diffs (15 lines):

diff -r a81aefcef6f9 -r 9bb24e6edc35 src/arch/sparc/isa/formats/branch.isa
--- a/src/arch/sparc/isa/formats/branch.isa Fri Jun 10 03:49:23 2011 -0400
+++ b/src/arch/sparc/isa/formats/branch.isa Fri Jun 10 22:15:32 2011 -0400
@@ -262,8 +262,9 @@
 let {{
 def doBranch(name, Name, base, cond,
 code, annul_code, fail, annul_fail, opt_flags):
-if "IsIndirectControl" not in opt_flags:
-   opt_flags += ('IsDirectControl', )
+#@todo: add flags and branchTarget() for DirectCntrl branches
+#   the o3 model can take advantage of this annotation if
+#   done correctly
 
 iop = InstObjParams(name, Name, base,
 {"code": code,
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Cron /z/m5/regression/do-regression quick

[Steve Reinhardt]

The regression runs as the 'm5test' user; if you tried to run under
/z/m5/regression as yourself or as root then it's probably running
into file/dir permissions problems.  I'll delete the build dir so we
shouldn't run into this again.

Usually it's best just to run the regressions in your own directory;
if you can run on zizzer then the regressions should run too.  You can
diff your tree with the one in /z/m5/regression/zizzer if necessary.
You don't have to wait more than 24 hours to see if the real
regression will work.

If you really need to rerun a regression the way cron does, you should use
sudo -u m5test -H /z/m5/regression/do-regression 
where  is either "quick" (what the nightly runs do) or
"--scratch all" (what happens Sat nights).

Steve

On Fri, Jun 10, 2011 at 1:16 AM, Korey Sewell  wrote:
> I was late in updating the repository. I think this may have happened since
> I was running stuff on zizzer while the regressions were loading up.  What's
> the method of choice for rerunning the do-regression script?
>
> Also, when updating the simple cpu regressions, I had to "hg merge" the
> changesets, so it seems I had a merge that didnt propagate through.
>
> I'm finally able to regenerate the o3-timing error seen in the regressions.
> I wont be able to fix those 2 regressions just this second, but the
> simple-cpu ones should be updated and when I get into the lab today, I'll
> look again into the O3 ones and see what happened.
>
>
> On Fri, Jun 10, 2011 at 3:02 AM, Cron Daemon 
> wrote:
>
>> scons: *** Cannot duplicate `src/SConscript' in `build/SPARC_SE': None.
>>  Stop.
>>
>> See /z/m5/regression/regress-2011-06-10-03:00:01 for details.
>>
>> ___
>> gem5-dev mailing list
>> gem5-dev@m5sim.org
>> http://m5sim.org/mailman/listinfo/gem5-dev
>>
>
>
>
> --
> - Korey
> ___
> gem5-dev mailing list
> gem5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/gem5-dev
>
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Cron /z/m5/regression/do-regression quick

[Gabe Black]

Merging the regression output (mainly stats) is probably not going to do
what you want, so if those files had to be merged then that's probably
part of the problem.

Gabe

On 06/10/11 01:16, Korey Sewell wrote:
> I was late in updating the repository. I think this may have happened since
> I was running stuff on zizzer while the regressions were loading up.  What's
> the method of choice for rerunning the do-regression script?
>
> Also, when updating the simple cpu regressions, I had to "hg merge" the
> changesets, so it seems I had a merge that didnt propagate through.
>
> I'm finally able to regenerate the o3-timing error seen in the regressions.
> I wont be able to fix those 2 regressions just this second, but the
> simple-cpu ones should be updated and when I get into the lab today, I'll
> look again into the O3 ones and see what happened.
>
>
> On Fri, Jun 10, 2011 at 3:02 AM, Cron Daemon 
> wrote:
>
>> scons: *** Cannot duplicate `src/SConscript' in `build/SPARC_SE': None.
>>  Stop.
>>
>> See /z/m5/regression/regress-2011-06-10-03:00:01 for details.
>>
>> ___
>> gem5-dev mailing list
>> gem5-dev@m5sim.org
>> http://m5sim.org/mailman/listinfo/gem5-dev
>>
>
>

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Ruby: Token Coherence and Functional Access

[Nilay Vaish]

Brad, in the token coherence protocol, the l2 cache controller moves from 
state O to I and sends data to the memory. I think this particular 
transition is may pose a problem in enabling functional accesses for the 
protocol. The problem, I think, is that both the directory and the cache 
controller are in stable states even though there is data travelling in 
the network. This means that both the controllers will allow a 
functional write to go ahead. But then the data will be over written by 
the value sent from the l2 controller to the directory controller.


My understanding of the protocol implementation is close to \epsilon. I 
think this is what I observed today in the morning. Do think this 
understanding is correct?


--
Nilay
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Cron /z/m5/regression/do-regression quick

[Korey Sewell]

I was late in updating the repository. I think this may have happened since
I was running stuff on zizzer while the regressions were loading up.  What's
the method of choice for rerunning the do-regression script?

Also, when updating the simple cpu regressions, I had to "hg merge" the
changesets, so it seems I had a merge that didnt propagate through.

I'm finally able to regenerate the o3-timing error seen in the regressions.
I wont be able to fix those 2 regressions just this second, but the
simple-cpu ones should be updated and when I get into the lab today, I'll
look again into the O3 ones and see what happened.


On Fri, Jun 10, 2011 at 3:02 AM, Cron Daemon wrote:

> scons: *** Cannot duplicate `src/SConscript' in `build/SPARC_SE': None.
>  Stop.
>
> See /z/m5/regression/regress-2011-06-10-03:00:01 for details.
>
> ___
> gem5-dev mailing list
> gem5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/gem5-dev
>



-- 
- Korey
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] changeset in gem5: sparc: merge regr. updates w/last update

[Korey Sewell]

changeset a81aefcef6f9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a81aefcef6f9
description:
sparc: merge regr. updates w/last update

diffstat:

 src/arch/sparc/isa/decoder.isa  |   6 +-
 src/arch/sparc/isa/formats/branch.isa   |   5 ++
 src/arch/sparc/isa/formats/mem/basicmem.isa |   6 ++
 src/arch/sparc/isa/formats/mem/swap.isa |   2 +-
 src/arch/sparc/isa/formats/mem/util.isa |  26 ++
 src/arch/sparc/mt.hh|  71 +
 src/arch/sparc/registers.hh |   2 +
 src/cpu/inorder/cpu.cc  |   1 +
 src/cpu/inorder/inorder_dyn_inst.cc |  19 +++
 9 files changed, 134 insertions(+), 4 deletions(-)

diffs (274 lines):

diff -r ce61b7a13407 -r a81aefcef6f9 src/arch/sparc/isa/decoder.isa
--- a/src/arch/sparc/isa/decoder.isaFri Jun 10 03:45:24 2011 -0400
+++ b/src/arch/sparc/isa/decoder.isaFri Jun 10 03:49:23 2011 -0400
@@ -141,7 +141,7 @@
 IntReg midVal;
 R15 = midVal = (Pstate<3:> ? (PC)<31:0> : PC);
 NNPC = midVal + disp;
-}});
+}},None, None, IsIndirectControl, IsCall);
 0x2: decode OP3 {
 format IntOp {
 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
@@ -1005,7 +1005,7 @@
 Rd = PC;
 NNPC = target;
 }
-}});
+}}, IsUncondControl, IsIndirectControl);
 0x39: Branch::return({{
 Addr target = Rs1 + Rs2_or_imm13;
 if (fault == NoFault) {
@@ -1025,7 +1025,7 @@
 Canrestore = Canrestore - 1;
 }
 }
-}});
+}}, IsUncondControl, IsIndirectControl, IsReturn);
 0x3A: decode CC
 {
 0x0: Trap::tcci({{
diff -r ce61b7a13407 -r a81aefcef6f9 src/arch/sparc/isa/formats/branch.isa
--- a/src/arch/sparc/isa/formats/branch.isa Fri Jun 10 03:45:24 2011 -0400
+++ b/src/arch/sparc/isa/formats/branch.isa Fri Jun 10 03:49:23 2011 -0400
@@ -262,6 +262,9 @@
 let {{
 def doBranch(name, Name, base, cond,
 code, annul_code, fail, annul_fail, opt_flags):
+if "IsIndirectControl" not in opt_flags:
+   opt_flags += ('IsDirectControl', )
+
 iop = InstObjParams(name, Name, base,
 {"code": code,
  "fail": fail,
@@ -289,12 +292,14 @@
 return (header_output, decoder_output, exec_output, decode_block)
 
 def doCondBranch(name, Name, base, cond, code, opt_flags):
+opt_flags += ('IsCondControl', )
 return doBranch(name, Name, base, cond, code, code,
 'NNPC = NNPC; NPC = NPC;\n',
 'NNPC = NPC + 8; NPC = NPC + 4;\n',
 opt_flags)
 
 def doUncondBranch(name, Name, base, code, annul_code, opt_flags):
+opt_flags += ('IsUncondControl', )
 return doBranch(name, Name, base, "true", code, annul_code,
 ";", ";", opt_flags)
 
diff -r ce61b7a13407 -r a81aefcef6f9 src/arch/sparc/isa/formats/mem/basicmem.isa
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa   Fri Jun 10 03:45:24 
2011 -0400
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa   Fri Jun 10 03:49:23 
2011 -0400
@@ -1,3 +1,5 @@
+// -*- mode:c++ -*-
+
 // Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
@@ -45,6 +47,8 @@
 
 %(BasicExecDeclare)s
 
+%(EACompDeclare)s
+
 %(InitiateAccDeclare)s
 
 %(CompleteAccDeclare)s
@@ -69,6 +73,8 @@
 exec_output = doDualSplitExecute(code, postacc_code, addrCalcReg,
 addrCalcImm, execute, faultCode, name, name + "Imm",
 Name, Name + "Imm", asi, opt_flags)
+exec_output +=  EACompExecute.subst(iop);
+exec_output +=  EACompExecute.subst(iop_imm);
 return (header_output, decoder_output, exec_output, decode_block)
 }};
 
diff -r ce61b7a13407 -r a81aefcef6f9 src/arch/sparc/isa/formats/mem/swap.isa
--- a/src/arch/sparc/isa/formats/mem/swap.isa   Fri Jun 10 03:45:24 2011 -0400
+++ b/src/arch/sparc/isa/formats/mem/swap.isa   Fri Jun 10 03:49:23 2011 -0400
@@ -163,7 +163,7 @@
 "EA_trunc" : TruncateEA}
 exec_output = doSplitExecute(execute, name, Name, mem_flags,
 ["IsStoreConditional"], microParams);
-return (header_output, decoder_output, exec_output, decode_block)
+return (header_output, decoder_output, exec_output + 
EACompExecute.subst(iop), decode_block)
 }};
 
 
diff -r ce61b7a13407 -r a81aefcef6f9 src/arch/sparc/isa/formats/mem/util.isa
--- a/src/arch/sparc/isa/formats/mem/util.isa   Fri Jun 10 03:45:24 2011 -0400
+++ b/src/arch/sparc/isa/formats/mem/util.isa   Fri Jun 10 03:49:23 2011 -0400
@@ -260,6 +260,32 @@
 }
 }};
 
+def template EACompExecute {{
+Fault
+%(class_name)s::eaComp(%(CPU_exe

[gem5-dev] changeset in gem5: sparc: update simple cpu regressions

[Korey Sewell]

changeset ce61b7a13407 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ce61b7a13407
description:
sparc: update simple cpu regressions
use stats file generated by zizzer

diffstat:

 tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt   
 |42 +-
 tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt  
 |42 +-
 tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt   
 |   386 +-
 tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
 |42 +-
 tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
 |   390 +-
 
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt 
|  1206 
 
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt 
|  1496 +-
 7 files changed, 1802 insertions(+), 1802 deletions(-)

diffs (truncated from 3865 to 300 lines):

diff -r 30daf1dd5c91 -r ce61b7a13407 
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt  Wed Jun 
08 11:58:09 2011 -0500
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt  Fri Jun 
10 03:45:24 2011 -0400
@@ -1,34 +1,34 @@
 
 -- Begin Simulation Statistics --
-host_inst_rate   4684   # 
Simulator instruction rate (inst/s)
-host_mem_usage 195500   # 
Number of bytes of host memory used
-host_seconds 1.14   # 
Real time elapsed on the host
-host_tick_rate2368799   # 
Simulator tick rate (ticks/s)
-sim_freq 1   # 
Frequency of simulated ticks
-sim_insts5340   # 
Number of instructions simulated
 sim_seconds  0.03   # 
Number of seconds simulated
 sim_ticks 2701000   # 
Number of ticks simulated
-system.cpu.idle_fraction0   # 
Percentage of idle cycles
-system.cpu.not_idle_fraction1   # 
Percentage of non-idle cycles
+sim_freq 1   # 
Frequency of simulated ticks
+host_inst_rate 639191   # 
Simulator instruction rate (inst/s)
+host_tick_rate  322368277   # 
Simulator tick rate (ticks/s)
+host_mem_usage 216400   # 
Number of bytes of host memory used
+host_seconds 0.01   # 
Real time elapsed on the host
+sim_insts5340   # 
Number of instructions simulated
+system.cpu.workload.num_syscalls   11   # 
Number of system calls
 system.cpu.numCycles 5403   # 
number of cpu cycles simulated
+system.cpu.numWorkItemsStarted  0   # 
number of work items this cpu started
 system.cpu.numWorkItemsCompleted0   # 
number of work items this cpu completed
-system.cpu.numWorkItemsStarted  0   # 
number of work items this cpu started
-system.cpu.num_busy_cycles   5403   # 
Number of busy cycles
-system.cpu.num_conditional_control_insts0   # 
number of instructions that are conditional controls
+system.cpu.num_insts 5340   # 
Number of instructions executed
+system.cpu.num_int_alu_accesses  4517   # 
Number of integer alu accesses
 system.cpu.num_fp_alu_accesses  0   # 
Number of float alu accesses
+system.cpu.num_func_calls 146   # 
number of times a function call or return occured
+system.cpu.num_conditional_control_insts  774   # 
number of instructions that are conditional controls
+system.cpu.num_int_insts 4517   # 
number of integer instructions
 system.cpu.num_fp_insts 0   # 
number of float instructions
+system.cpu.num_int_register_reads   10620   # 
number of times the integer registers were read
+system.cpu.num_int_register_writes   4859   # 
number of times the integer