changeset 5955406f7ed0 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=5955406f7ed0 description: Ruby: Convert CacheRequestType to RubyRequestType This patch converts CacheRequestType to RubyRequestType so that both the protocol dependent and independent code makes use of the same request type.
diffstat: src/mem/protocol/MESI_CMP_directory-L1cache.sm | 12 ++-- src/mem/protocol/MI_example-cache.sm | 10 +- src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 12 ++-- src/mem/protocol/MOESI_CMP_token-L1cache.sm | 24 ++++---- src/mem/protocol/MOESI_hammer-cache.sm | 14 ++-- src/mem/protocol/RubySlicc_Exports.sm | 28 ++++++---- src/mem/ruby/profiler/AccessTraceForAddress.cc | 8 +- src/mem/ruby/profiler/AccessTraceForAddress.hh | 4 +- src/mem/ruby/profiler/AddressProfiler.cc | 6 +- src/mem/ruby/profiler/AddressProfiler.hh | 2 +- src/mem/ruby/profiler/CacheProfiler.cc | 12 ++-- src/mem/ruby/profiler/CacheProfiler.hh | 4 +- src/mem/ruby/profiler/Profiler.cc | 8 +- src/mem/ruby/profiler/Profiler.hh | 4 +- src/mem/ruby/recorder/CacheRecorder.hh | 2 +- src/mem/ruby/recorder/Tracer.hh | 2 +- src/mem/ruby/slicc_interface/RubyRequest.cc | 63 ------------------------- src/mem/ruby/slicc_interface/RubyRequest.hh | 18 +------ src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 2 +- src/mem/ruby/system/CacheMemory.cc | 16 +++--- src/mem/ruby/system/CacheMemory.hh | 6 +- src/mem/ruby/system/DMASequencer.cc | 10 +--- src/mem/ruby/system/Sequencer.cc | 16 +++--- src/mem/ruby/system/Sequencer.hh | 4 +- 24 files changed, 103 insertions(+), 184 deletions(-) diffs (truncated from 786 to 300 lines): diff -r b043c0efa024 -r 5955406f7ed0 src/mem/protocol/MESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Sat Mar 19 18:34:37 2011 -0500 +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Sat Mar 19 18:34:59 2011 -0500 @@ -183,15 +183,15 @@ } } - Event mandatory_request_type_to_event(CacheRequestType type) { - if (type == CacheRequestType:LD) { + Event mandatory_request_type_to_event(RubyRequestType type) { + if (type == RubyRequestType:LD) { return Event:Load; - } else if (type == CacheRequestType:IFETCH) { + } else if (type == RubyRequestType:IFETCH) { return Event:Ifetch; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) { return Event:Store; } else { - error("Invalid CacheRequestType"); + error("Invalid RubyRequestType"); } } @@ -273,7 +273,7 @@ // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache - if (in_msg.Type == CacheRequestType:IFETCH) { + if (in_msg.Type == RubyRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); diff -r b043c0efa024 -r 5955406f7ed0 src/mem/protocol/MI_example-cache.sm --- a/src/mem/protocol/MI_example-cache.sm Sat Mar 19 18:34:37 2011 -0500 +++ b/src/mem/protocol/MI_example-cache.sm Sat Mar 19 18:34:59 2011 -0500 @@ -84,15 +84,15 @@ } // FUNCTIONS - Event mandatory_request_type_to_event(CacheRequestType type) { - if (type == CacheRequestType:LD) { + Event mandatory_request_type_to_event(RubyRequestType type) { + if (type == RubyRequestType:LD) { return Event:Load; - } else if (type == CacheRequestType:IFETCH) { + } else if (type == RubyRequestType:IFETCH) { return Event:Ifetch; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) { return Event:Store; } else { - error("Invalid CacheRequestType"); + error("Invalid RubyRequestType"); } } diff -r b043c0efa024 -r 5955406f7ed0 src/mem/protocol/MOESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sat Mar 19 18:34:37 2011 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sat Mar 19 18:34:59 2011 -0500 @@ -194,15 +194,15 @@ } } - Event mandatory_request_type_to_event(CacheRequestType type) { - if (type == CacheRequestType:LD) { + Event mandatory_request_type_to_event(RubyRequestType type) { + if (type == RubyRequestType:LD) { return Event:Load; - } else if (type == CacheRequestType:IFETCH) { + } else if (type == RubyRequestType:IFETCH) { return Event:Ifetch; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) { return Event:Store; } else { - error("Invalid CacheRequestType"); + error("Invalid RubyRequestType"); } } @@ -309,7 +309,7 @@ // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache - if (in_msg.Type == CacheRequestType:IFETCH) { + if (in_msg.Type == RubyRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); diff -r b043c0efa024 -r 5955406f7ed0 src/mem/protocol/MOESI_CMP_token-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sat Mar 19 18:34:37 2011 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sat Mar 19 18:34:59 2011 -0500 @@ -341,31 +341,31 @@ } } - Event mandatory_request_type_to_event(CacheRequestType type) { - if (type == CacheRequestType:LD) { + Event mandatory_request_type_to_event(RubyRequestType type) { + if (type == RubyRequestType:LD) { return Event:Load; - } else if (type == CacheRequestType:IFETCH) { + } else if (type == RubyRequestType:IFETCH) { return Event:Ifetch; - } else if (type == CacheRequestType:ST) { + } else if (type == RubyRequestType:ST) { return Event:Store; - } else if (type == CacheRequestType:ATOMIC) { + } else if (type == RubyRequestType:ATOMIC) { if (no_mig_atomic) { return Event:Atomic; } else { return Event:Store; } } else { - error("Invalid CacheRequestType"); + error("Invalid RubyRequestType"); } } - AccessType cache_request_type_to_access_type(CacheRequestType type) { - if ((type == CacheRequestType:LD) || (type == CacheRequestType:IFETCH)) { + AccessType cache_request_type_to_access_type(RubyRequestType type) { + if ((type == RubyRequestType:LD) || (type == RubyRequestType:IFETCH)) { return AccessType:Read; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) { return AccessType:Write; } else { - error("Invalid CacheRequestType"); + error("Invalid RubyRequestType"); } } @@ -629,7 +629,7 @@ TBE tbe := L1_TBEs[in_msg.LineAddress]; - if (in_msg.Type == CacheRequestType:IFETCH) { + if (in_msg.Type == RubyRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); @@ -1313,7 +1313,7 @@ peek(mandatoryQueue_in, CacheMsg) { tbe.PC := in_msg.ProgramCounter; tbe.AccessType := cache_request_type_to_access_type(in_msg.Type); - if (in_msg.Type == CacheRequestType:ATOMIC) { + if (in_msg.Type == RubyRequestType:ATOMIC) { tbe.IsAtomic := true; } tbe.Prefetch := in_msg.Prefetch; diff -r b043c0efa024 -r 5955406f7ed0 src/mem/protocol/MOESI_hammer-cache.sm --- a/src/mem/protocol/MOESI_hammer-cache.sm Sat Mar 19 18:34:37 2011 -0500 +++ b/src/mem/protocol/MOESI_hammer-cache.sm Sat Mar 19 18:34:59 2011 -0500 @@ -214,15 +214,15 @@ } } - Event mandatory_request_type_to_event(CacheRequestType type) { - if (type == CacheRequestType:LD) { + Event mandatory_request_type_to_event(RubyRequestType type) { + if (type == RubyRequestType:LD) { return Event:Load; - } else if (type == CacheRequestType:IFETCH) { + } else if (type == RubyRequestType:IFETCH) { return Event:Ifetch; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) { return Event:Store; } else { - error("Invalid CacheRequestType"); + error("Invalid RubyRequestType"); } } @@ -359,7 +359,7 @@ // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache TBE tbe := TBEs[in_msg.LineAddress]; - if (in_msg.Type == CacheRequestType:IFETCH) { + if (in_msg.Type == RubyRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); @@ -700,7 +700,7 @@ cache_entry.DataBlk); cache_entry.Dirty := true; - if (in_msg.Type == CacheRequestType:ATOMIC) { + if (in_msg.Type == RubyRequestType:ATOMIC) { cache_entry.AtomicAccessed := true; } } diff -r b043c0efa024 -r 5955406f7ed0 src/mem/protocol/RubySlicc_Exports.sm --- a/src/mem/protocol/RubySlicc_Exports.sm Sat Mar 19 18:34:37 2011 -0500 +++ b/src/mem/protocol/RubySlicc_Exports.sm Sat Mar 19 18:34:59 2011 -0500 @@ -103,16 +103,22 @@ ProtocolStall, desc="Protocol specified stall"; } -// CacheRequestType -enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") { - LD, desc="Load"; - ST, desc="Store"; - ATOMIC, desc="Atomic Load/Store"; - IFETCH, desc="Instruction fetch"; - IO, desc="I/O"; - REPLACEMENT, desc="Replacement"; - COMMIT, desc="Commit version"; - NULL, desc="Invalid request type"; +// RubyRequestType +enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") { + LD, desc="Load"; + ST, desc="Store"; + ATOMIC, desc="Atomic Load/Store"; + IFETCH, desc="Instruction fetch"; + IO, desc="I/O"; + REPLACEMENT, desc="Replacement"; + Load_Linked, desc=""; + Store_Conditional, desc=""; + RMW_Read, desc=""; + RMW_Write, desc=""; + Locked_RMW_Read, desc=""; + Locked_RMW_Write, desc=""; + COMMIT, desc="Commit version"; + NULL, desc="Invalid request type"; } enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") { @@ -211,7 +217,7 @@ structure(CacheMsg, desc="...", interface="Message") { Address LineAddress, desc="Line address for this request"; Address PhysicalAddress, desc="Physical address for this request"; - CacheRequestType Type, desc="Type of request (LD, ST, etc)"; + RubyRequestType Type, desc="Type of request (LD, ST, etc)"; Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; RubyAccessMode AccessMode, desc="user/supervisor access type"; int Size, desc="size in bytes of access"; diff -r b043c0efa024 -r 5955406f7ed0 src/mem/ruby/profiler/AccessTraceForAddress.cc --- a/src/mem/ruby/profiler/AccessTraceForAddress.cc Sat Mar 19 18:34:37 2011 -0500 +++ b/src/mem/ruby/profiler/AccessTraceForAddress.cc Sat Mar 19 18:34:59 2011 -0500 @@ -58,17 +58,17 @@ } void -AccessTraceForAddress::update(CacheRequestType type, +AccessTraceForAddress::update(RubyRequestType type, RubyAccessMode access_mode, NodeID cpu, bool sharing_miss) { m_touched_by.add(cpu); m_total++; - if(type == CacheRequestType_ATOMIC) { + if(type == RubyRequestType_ATOMIC) { m_atomics++; - } else if(type == CacheRequestType_LD){ + } else if(type == RubyRequestType_LD){ m_loads++; - } else if (type == CacheRequestType_ST){ + } else if (type == RubyRequestType_ST){ m_stores++; } else { // ERROR_MSG("Trying to add invalid access to trace"); diff -r b043c0efa024 -r 5955406f7ed0 src/mem/ruby/profiler/AccessTraceForAddress.hh --- a/src/mem/ruby/profiler/AccessTraceForAddress.hh Sat Mar 19 18:34:37 2011 -0500 +++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh Sat Mar 19 18:34:59 2011 -0500 @@ -32,7 +32,7 @@ #include <iostream> #include "mem/protocol/RubyAccessMode.hh" -#include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/RubyRequestType.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Set.hh" @@ -50,7 +50,7 @@ ~AccessTraceForAddress(); void setAddress(const Address& addr) { m_addr = addr; } - void update(CacheRequestType type, RubyAccessMode access_mode, NodeID cpu, + void update(RubyRequestType type, RubyAccessMode access_mode, NodeID cpu, bool sharing_miss); int getTotal() const; int getSharing() const { return m_sharing; } diff -r b043c0efa024 -r 5955406f7ed0 src/mem/ruby/profiler/AddressProfiler.cc --- a/src/mem/ruby/profiler/AddressProfiler.cc Sat Mar 19 18:34:37 2011 -0500 +++ b/src/mem/ruby/profiler/AddressProfiler.cc Sat Mar 19 18:34:59 2011 -0500 @@ -257,7 +257,7 @@ m_getx_sharing_histogram.add(num_indirections); bool indirection_miss = (num_indirections > 0); - addTraceSample(datablock, PC, CacheRequestType_ST, RubyAccessMode(0), + addTraceSample(datablock, PC, RubyRequestType_ST, RubyAccessMode(0), requestor, indirection_miss); } @@ -274,13 +274,13 @@ m_gets_sharing_histogram.add(num_indirections); _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev