changeset e21f6e70169e in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=e21f6e70169e description: Ruby: Remove CacheMsg class from SLICC The goal of the patch is to do away with the CacheMsg class currently in use in coherence protocols. In place of CacheMsg, the RubyRequest class will used. This class is already present in slicc_interface/RubyRequest.hh. In fact, objects of class CacheMsg are generated by copying values from a RubyRequest object.
diffstat: src/mem/protocol/MESI_CMP_directory-L1cache.sm | 12 +- src/mem/protocol/MI_example-cache.sm | 6 +- src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 10 +- src/mem/protocol/MOESI_CMP_token-L1cache.sm | 12 +- src/mem/protocol/MOESI_hammer-cache.sm | 8 +- src/mem/protocol/Network_test-cache.sm | 4 +- src/mem/protocol/RubySlicc_Exports.sm | 11 - src/mem/protocol/RubySlicc_Profiler.sm | 4 +- src/mem/protocol/RubySlicc_Types.sm | 12 +- src/mem/ruby/profiler/AddressProfiler.cc | 2 +- src/mem/ruby/profiler/AddressProfiler.hh | 2 +- src/mem/ruby/profiler/Profiler.cc | 4 +- src/mem/ruby/profiler/Profiler.hh | 4 +- src/mem/ruby/recorder/TraceRecord.cc | 2 +- src/mem/ruby/slicc_interface/RubyRequest.cc | 41 +-- src/mem/ruby/slicc_interface/RubyRequest.hh | 104 +++++++- src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh | 4 +- src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 2 - src/mem/ruby/system/CacheMemory.cc | 2 +- src/mem/ruby/system/CacheMemory.hh | 4 +- src/mem/ruby/system/DMASequencer.cc | 6 +- src/mem/ruby/system/RubyPort.cc | 2 +- src/mem/ruby/system/Sequencer.cc | 116 +++++----- 23 files changed, 208 insertions(+), 166 deletions(-) diffs (truncated from 893 to 300 lines): diff -r 2c47dc111abd -r e21f6e70169e src/mem/protocol/MESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Mon Mar 21 22:51:59 2011 -0400 +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Tue Mar 22 06:41:54 2011 -0500 @@ -267,9 +267,9 @@ } // Mandatory Queue betweens Node's CPU and it's L1 caches - in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") { + in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") { + peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache @@ -338,7 +338,7 @@ // ACTIONS action(a_issueGETS, "a", desc="Issue GETS") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETS; @@ -355,7 +355,7 @@ } action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GET_INSTR; @@ -373,7 +373,7 @@ action(b_issueGETX, "b", desc="Issue GETX") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETX; @@ -391,7 +391,7 @@ } action(c_issueUPGRADE, "c", desc="Issue GETX") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { enqueue(requestIntraChipL1Network_out, RequestMsg, latency= l1_request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:UPGRADE; diff -r 2c47dc111abd -r e21f6e70169e src/mem/protocol/MI_example-cache.sm --- a/src/mem/protocol/MI_example-cache.sm Mon Mar 21 22:51:59 2011 -0400 +++ b/src/mem/protocol/MI_example-cache.sm Tue Mar 22 06:41:54 2011 -0500 @@ -181,9 +181,9 @@ } // Mandatory Queue - in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") { + in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") { + peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { Entry cache_entry := getCacheEntry(in_msg.LineAddress); if (is_invalid(cache_entry) && @@ -281,7 +281,7 @@ } action(p_profileMiss, "p", desc="Profile cache miss") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { cacheMemory.profileMiss(in_msg); } } diff -r 2c47dc111abd -r e21f6e70169e src/mem/protocol/MOESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Mon Mar 21 22:51:59 2011 -0400 +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Tue Mar 22 06:41:54 2011 -0500 @@ -303,9 +303,9 @@ // Nothing from the unblock network // Mandatory Queue betweens Node's CPU and it's L1 caches - in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") { + in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") { + peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache @@ -380,7 +380,7 @@ // ACTIONS action(a_issueGETS, "a", desc="Issue GETS") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { enqueue(requestNetwork_out, RequestMsg, latency= request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETS; @@ -396,7 +396,7 @@ } action(b_issueGETX, "b", desc="Issue GETX") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { enqueue(requestNetwork_out, RequestMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETX; @@ -820,7 +820,7 @@ action(uu_profileMiss, "\u", desc="Profile the demand miss") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { // profile_miss(in_msg); } } diff -r 2c47dc111abd -r e21f6e70169e src/mem/protocol/MOESI_CMP_token-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Mon Mar 21 22:51:59 2011 -0400 +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Tue Mar 22 06:41:54 2011 -0500 @@ -622,9 +622,9 @@ } // Mandatory Queue - in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...", rank=0) { + in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank=0) { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") { + peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache TBE tbe := L1_TBEs[in_msg.LineAddress]; @@ -1310,7 +1310,7 @@ L1_TBEs.allocate(address); set_tbe(L1_TBEs[address]); tbe.IssueCount := 0; - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { tbe.PC := in_msg.ProgramCounter; tbe.AccessType := cache_request_type_to_access_type(in_msg.Type); if (in_msg.Type == RubyRequestType:ATOMIC) { @@ -1323,7 +1323,7 @@ } action(ta_traceStalledAddress, "ta", desc="Trace Stalled Address") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { APPEND_TRANSITION_COMMENT(in_msg.LineAddress); } } @@ -1499,7 +1499,7 @@ } action(uu_profileMiss, "\u", desc="Profile the demand miss") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { if (L1DcacheMemory.isTagPresent(address)) { L1DcacheMemory.profileMiss(in_msg); } else { @@ -1516,7 +1516,7 @@ } action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { APPEND_TRANSITION_COMMENT(in_msg.LineAddress); } stall_and_wait(mandatoryQueue_in, address); diff -r 2c47dc111abd -r e21f6e70169e src/mem/protocol/MOESI_hammer-cache.sm --- a/src/mem/protocol/MOESI_hammer-cache.sm Mon Mar 21 22:51:59 2011 -0400 +++ b/src/mem/protocol/MOESI_hammer-cache.sm Tue Mar 22 06:41:54 2011 -0500 @@ -352,9 +352,9 @@ // Nothing from the request network // Mandatory Queue - in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...", rank=0) { + in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank=0) { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") { + peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache TBE tbe := TBEs[in_msg.LineAddress]; @@ -695,7 +695,7 @@ action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { sequencer.writeCallback(address, testAndClearLocalHit(cache_entry), cache_entry.DataBlk); @@ -1022,7 +1022,7 @@ } action(uu_profileMiss, "\u", desc="Profile the demand miss") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { if (L1IcacheMemory.isTagPresent(address)) { L1IcacheMemory.profileMiss(in_msg); } else if (L1DcacheMemory.isTagPresent(address)) { diff -r 2c47dc111abd -r e21f6e70169e src/mem/protocol/Network_test-cache.sm --- a/src/mem/protocol/Network_test-cache.sm Mon Mar 21 22:51:59 2011 -0400 +++ b/src/mem/protocol/Network_test-cache.sm Tue Mar 22 06:41:54 2011 -0500 @@ -132,9 +132,9 @@ out_port(responseNetwork_out, RequestMsg, responseFromCache); // Mandatory Queue - in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") { + in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, getCacheEntry(in_msg.LineAddress), diff -r 2c47dc111abd -r e21f6e70169e src/mem/protocol/RubySlicc_Exports.sm --- a/src/mem/protocol/RubySlicc_Exports.sm Mon Mar 21 22:51:59 2011 -0400 +++ b/src/mem/protocol/RubySlicc_Exports.sm Tue Mar 22 06:41:54 2011 -0500 @@ -214,17 +214,6 @@ } // CacheMsg -structure(CacheMsg, desc="...", interface="Message") { - Address LineAddress, desc="Line address for this request"; - Address PhysicalAddress, desc="Physical address for this request"; - RubyRequestType Type, desc="Type of request (LD, ST, etc)"; - Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; - RubyAccessMode AccessMode, desc="user/supervisor access type"; - int Size, desc="size in bytes of access"; - PrefetchBit Prefetch, desc="Is this a prefetch request"; -} - -// CacheMsg structure(SequencerMsg, desc="...", interface="Message") { Address LineAddress, desc="Line address for this request"; Address PhysicalAddress, desc="Physical address for this request"; diff -r 2c47dc111abd -r e21f6e70169e src/mem/protocol/RubySlicc_Profiler.sm --- a/src/mem/protocol/RubySlicc_Profiler.sm Mon Mar 21 22:51:59 2011 -0400 +++ b/src/mem/protocol/RubySlicc_Profiler.sm Tue Mar 22 06:41:54 2011 -0500 @@ -34,10 +34,10 @@ void profileMemoryCLBsize(int size, int numStaleI); // used by 2level exclusive cache protocols -void profile_miss(CacheMsg msg); +void profile_miss(RubyRequest msg); // used by non-fast path protocols -void profile_L1Cache_miss(CacheMsg msg, NodeID l1cacheID); +void profile_L1Cache_miss(RubyRequest msg, NodeID l1cacheID); // used by CMP protocols void profile_request(std::string L1CacheStateStr, std::string L2CacheStateStr, diff -r 2c47dc111abd -r e21f6e70169e src/mem/protocol/RubySlicc_Types.sm --- a/src/mem/protocol/RubySlicc_Types.sm Mon Mar 21 22:51:59 2011 -0400 +++ b/src/mem/protocol/RubySlicc_Types.sm Tue Mar 22 06:41:54 2011 -0500 @@ -109,6 +109,16 @@ void profileNack(Address, int, int, uint64); } +structure(RubyRequest, desc="...", interface="Message", external="yes") { + Address LineAddress, desc="Line address for this request"; + Address PhysicalAddress, desc="Physical address for this request"; + RubyRequestType Type, desc="Type of request (LD, ST, etc)"; + Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; + RubyAccessMode AccessMode, desc="user/supervisor access type"; + int Size, desc="size in bytes of access"; + PrefetchBit Prefetch, desc="Is this a prefetch request"; +} + external_type(AbstractEntry, primitive="yes"); structure (DirectoryMemory, external = "yes") { @@ -126,7 +136,7 @@ void deallocate(Address); AbstractCacheEntry lookup(Address); bool isTagPresent(Address); - void profileMiss(CacheMsg); + void profileMiss(RubyRequest); void profileGenericRequest(GenericRequestType, RubyAccessMode, diff -r 2c47dc111abd -r e21f6e70169e src/mem/ruby/profiler/AddressProfiler.cc --- a/src/mem/ruby/profiler/AddressProfiler.cc Mon Mar 21 22:51:59 2011 -0400 +++ b/src/mem/ruby/profiler/AddressProfiler.cc Tue Mar 22 06:41:54 2011 -0500 @@ -29,7 +29,7 @@ #include <vector> #include "base/stl_helpers.hh" -#include "mem/protocol/CacheMsg.hh" +#include "mem/protocol/RubyRequest.hh" #include "mem/ruby/profiler/AddressProfiler.hh" #include "mem/ruby/profiler/Profiler.hh" #include "mem/ruby/system/System.hh" diff -r 2c47dc111abd -r e21f6e70169e src/mem/ruby/profiler/AddressProfiler.hh --- a/src/mem/ruby/profiler/AddressProfiler.hh Mon Mar 21 22:51:59 2011 -0400 +++ b/src/mem/ruby/profiler/AddressProfiler.hh Tue Mar 22 06:41:54 2011 -0500 @@ -33,7 +33,7 @@ #include "base/hashmap.hh" _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev