Re: [gem5-users] ARM instruction set

[Ali Saidi]

The format calls a function that is defined by (not in) the insts code. The 
templates are just that boilerplate code that gets string substitutions to turn 
it into the what ends up in build/ARM/arch/arm/generated/*. Pretty much insts 
instantiates string substituted templates from templates that are decoded by 
formats.

Ali

On Jun 26, 2013, at 9:10 AM, Jianghao  wrote:

> Thanks Ali. You are always helpful.
> 
> Inside buildMultInst(), there is call to templates defined in 
> src/arch/arm/isa/templates/multi.isa, but I cannot find connection between 
> src/arch/arm/isa/format/mult.isa and src/arch/arm/isa/insts/mult.isa.
> 
> So what's the link among those files under /format, /templates and /insts 
> directories?
> 
> 
> On 6/25/2013 11:32 PM, Ali Saidi wrote:
>> That code ends up in src/arch/arm/isa/insts/mult.isa which ultimately calls 
>> buildMultInst() and that function emits two versions of Mul one that sets 
>> the condition codes and one that does not. The prior has Cc appended to the 
>> name.
>> 
>> Ali
>> 
>> On Jun 24, 2013, at 4:13 PM, Jianghao  wrote:
>> 
>>> I have a questions about ARM ISA implementation.
>>> From the document, instruction "format" is basically a Python function to 
>>> generate up to four pieces of C++ code.
>>> If it's nested format structure like following code, which one will be 
>>> used, DataOp, ArmMultAndMultAcc or both for the multiply instruction?
>>> 
>>> decode COND_CODE {
>>> 0xF: ArmUnconditional::armUnconditional();
>>> default: decode ENCODING {
>>> format DataOp {
>>> 0x0: decode SEVEN_AND_FOUR {
>>> 1: decode MISC_OPCODE {
>>> 0x9: decode PREPOST {
>>> 0: ArmMultAndMultAcc::armMultAndMultAcc();
>>> 1: ArmSyncMem::armSyncMem();
>>> }
>>> 0xb, 0xd, 0xf: AddrMode3::addrMode3();
>>> }
>>> 
>>> When I take a look of ArmMultAndMultAcc format code, there are return 
>>> statements like following 
>>> "return new MulCc(machInst, rd, rm, rn);"
>>> What's the meaning of this? I even cannot grep any definition of MulCc in 
>>> src directory.
>>> 
>>> Thanks
>>> ___
>>> gem5-users mailing list
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>> 
>> 
>> 
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[gem5-users] Error--fatal: Ruby functional read failed for address 0x581bb000

[tejasi pimpalkhute]

Hi All,

I am getting the following error when I try to run gem5 with the command
line mentioned below-

fatal: Ruby functional read failed for address 0x581bb000
 @ cycle 4377668000
[recvFunctional:build/ALPHA_MESI_CMP_directory/mem/ruby/system/RubyPort.cc,
line 270]


my command line-
./build/ALPHA_MESI_CMP_directory/gem5.opt  configs/example/se.py -n 48
--cpu-type=detailed --clock=1GHz --topology=MeshDirSolo --caches
--cacheline_size=64 --l2cache --num-l2caches=16 --l1d_size=16kB
--l1i_size=16kB --l2_size=128kB --l1d_assoc=2 --l1i_assoc=2 --l2_assoc=2
--num-dirs=1 --mesh-rows=4 --ruby --garnet-network=fixed --rootdir="spec2k"
--benchmark="gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid;gcc;mgrid"
-I 100

Could anyone please guide me on how to fix this error?
I appreciate your response!
Thanks!

-- 
Tejasi
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Re: [gem5-users] Multiple Workloads/Benchmarks on a single CPU

[Nithesh Kurella]

Hi Ali

Thanks for your response. I will run in gdb for the the segmentation fault.
What about the problem of only one binary being able to get executed and
print? I observe the same problem when I run the simulator without smt and
in detailed CPU model with 2 cpu's. I am not able corner the bug as
everything works fine in timing CPU model. Any idea regarding this?

Thanks
Nithesh


>I don't know that anyone has really looked at SMT with the ARM ISA in
gem5. A good start to debugging the problem would be to >run the simulator
in gdb and see where you're getting a segmentation fault.
>
>Ali
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Re: [gem5-users] ARM instruction set

[Jianghao]

Thanks Ali. You are always helpful.

Inside buildMultInst(), there is call to templates defined in 
src/arch/arm/isa/templates/multi.isa, but I cannot find connection 
between src/arch/arm/isa/format/mult.isa and 
src/arch/arm/isa/insts/mult.isa.


So what's the link among those files under /format, /templates and 
/insts directories?



On 6/25/2013 11:32 PM, Ali Saidi wrote:
That code ends up in src/arch/arm/isa/insts/mult.isa which ultimately 
calls buildMultInst() and that function emits two versions of Mul one 
that sets the condition codes and one that does not. The prior has Cc 
appended to the name.


Ali

On Jun 24, 2013, at 4:13 PM, Jianghao > wrote:



I have a questions about ARM ISA implementation.
From the document, instruction "format" is basically a Python 
function to generate up to four pieces of C++ code.
If it's nested format structure like following code, which one will 
be used, DataOp, ArmMultAndMultAcc or both for the multiply instruction?


decode COND_CODE {
0xF: ArmUnconditional::armUnconditional();
default: decode ENCODING {
format DataOp {
0x0: decode SEVEN_AND_FOUR {
1: decode MISC_OPCODE {
0x9: decode PREPOST {
0: ArmMultAndMultAcc::armMultAndMultAcc();
1: ArmSyncMem::armSyncMem();
}
0xb, 0xd, 0xf: AddrMode3::addrMode3();
}

When I take a look of ArmMultAndMultAcc format code, there are return 
statements like following

"return new MulCc(machInst, rd, rm, rn);"
What's the meaning of this? I even cannot grep any definition of 
MulCc in src directory.


Thanks
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Re: [gem5-users] A Quick Question

[Andreas Hansson]

Hi Erfan,

Today you cannot connect two buses directly to each other. You will need to 
either insert a cache or bridge in between.

The error you see seems to suggest you have connected two ports on the buses to 
each other (which is causing the multiple-range issue).

Andreas

From: Erfan Azarkhish mailto:e.azarkh...@gmail.com>>
Reply-To: gem5 users mailing list 
mailto:gem5-users@gem5.org>>
Date: Wednesday, 26 June 2013 15:02
To: gem5 users mailto:gem5-users@gem5.org>>
Subject: [gem5-users] A Quick Question

Dear All,

I wanted to know if it is possible to connect two buses to each other. When I 
create the following topology:

Processor ---> MemBus1 ---> MemBus2 ---> SimpleMemory

I get the following error:

fatal: system.membus
1
has two ports with same range:
system.
membus2.slave[0]
system.
membus2.slave[0]

I
want to make a complex topology and I need to connect the buses to each other


T
hanks


--
Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEIS - University of Bologna, Italy

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[gem5-users] A Quick Question

[Erfan Azarkhish]

Dear All,

I wanted to know if it is possible to connect two buses to each other. When
I create the following topology:

Processor ---> MemBus1 ---> MemBus2 ---> SimpleMemory

I get the following error:

fatal: system.membus
1
has two ports with same range:
system.
membus2.slave[0]
system.
membus2.slave[0]

I
want to make a complex topology and I need to connect the buses to each
other


T
hanks


-- 
Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEIS - University of Bologna, Italy
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Re: [gem5-users] instruction size

[Xiangyang Guo]

By the way, from the source code, the instSize=sizeof(TheISA::Machinst),
and for the X86 ISA, Machinst is from the u_int64_t, which is 64 bits. So
could I know is the inst size is 8 bytes in Gem5 by default for X86 ISA?
Please correct me if I'm wrong. Thanks

Regards

Xiangyang


On Tue, Jun 25, 2013 at 2:48 PM, Xiangyang Guo  wrote:

> Hi, gem5-user,
>
> I want to collect the instruction size in X86. I printout the "instSize"
> in  src/cpu/o3/fetch_impl.hh. It shows that all the instruction size is
> 8, which means all the instruction is 64 bits. From my understanding, the
> instruction size should be variable in X86 ISA, So could anyone tell me why
> all the instruction size is same and it's 8? Thanks a lot.
>
> In addition, does the instruction size matter with the X86 mode. I mean if
> I choose another mode, such as "compatibly mode" by changing the configure
> in process.cc, should the instruction size change ? Actually, I changed the
> mode from "sixtyfourbitmode" to"compatibility mode", but the instruction
> size is still 8.
>
> Any hint is appreciable. Thank you for your time.
>
> Xiangyang
>
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