[gem5-users] Mounting second image FS

[George Michelogiannakis via gem5-users]

Hi all,

I have the standard setup with the x86 disk image containing parsec. I'm trying 
to add benchmarks and because that image has no more space, I created new 
images with the extra benchmarks. Those images don't have the OS, therefore the 
primary x86 image needs to boot and I need to mount the second image.

The only reference in the wiki I could find is that I have to add it to 
FSConfig.py or provide it as a --disk-image. Does that parameter take two image 
files?

Also, how do I mount it in the rcS file (from the m5 console)?

Thank you!
  George M___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Computing CPI Stack

[Vanchinathan Venkataramani via gem5-users]

Hi all

I would like to know how I can build up the CPI stack from gem5 statistics.

Thanks in advance
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Instcount <=1500 failing for a single core full system simulation

[Urmish Ajit Thakker via gem5-users]

Hi,

I was running the full system simulation for the newly released arm 64 
kernel and image. While running the simulation I encountered the 
following error -


gem5.opt: build/ARM/cpu/base_dyn_inst_impl.hh:123: void BaseDynInst< 
 >::initVars() [with Impl = O3CPUImpl]: 
Assertion `cpu->instcount <= 1500' failed.


The number of CPUs I use for simulation is only one (I use the dtb file 
part of the download package).


I have seen some related issues on the gem5 mailing list but from what I 
gathered they seem to be for multicore scenario.


This is the command that I give to run the simulation -

build/ARM/gem5.opt configs/example/fs.py --caches --cpu-type=DerivO3CPU 
--num-cpus=1 --machine-type=VExpress_EMM64 
--disk-image=/research/uthakker/gem5/arm_october_64/disks/arm_8gb 
--kernel=vmlinux.aarch64.20140821 
--dtb-filename=vexpress.aarch64.20140821.dtb 
--script=/research/uthakker/gem5/gem5/configs/boot/openCV.rcs


Any pointers as to why is this happening or how should I start debugging 
this isssue?


Regards,
Urmish
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Multi processor simulation in GEM5

[Kumail Ahmed via gem5-users]

Hello Everyone,

I'm a newbie to GEM5. I have some naive questions.


How can I run more than one application in multi-core on GEM5?

I mean.. I have 4 cores, and I want to run 4 applications on them.

=

Secondly, how is a normal CPU defined in SE mode. I mean how many L1 and L2
caches does it have, and how are they connected?


Best regards,
Kumail
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] DRAM memory access latency

[Prathap Kolakkampadath via gem5-users]

Thanks for your reply. I will try to verify this and also get back to you
with results once i run with your patch.

Regards,
Prathap

On Thu, Nov 6, 2014 at 2:30 PM, Andreas Hansson 
wrote:

>  Hi Prathap,
>
>  I suspect the answer to the mysterious 50 ns is due to the responses
> being sent back using a so called “queued port” in gem5. Thus, from the
> memory controller’s point of view the packet is all done, but is now
> waiting in the port until the crossbar can accept it. This queue can hold a
> number of packets if there has been a burst of responses that are trickling
> through the crossbar on their way back.
>
>  You can always run with some debug flags to verify this (XBar, DRAM,
> PacketQueue etc).
>
>  Coincidentally I have been working on a patch to remove this “invisible”
> queue and should hopefully have this on the review board shortly.
>
>  Andreas
>
>   From: Prathap Kolakkampadath 
> Date: Thursday, November 6, 2014 at 5:47 PM
> To: Andreas Hansson 
> Cc: gem5 users mailing list 
>
> Subject: Re: [gem5-users] DRAM memory access latency
>
>   Hello Andreas,
>
>  Thanks for your reply.
>
>
>  Ok. I got that the memory access latency indeed includes the queueing
> latency. And for the read/write request that miss the buffer has a static
> latency of  Static frontend latency + Static backend latency.
>
>
>  To summarize, the test i run is a latency benchmark which is a pointer
> chasing test(only one request at a time) , generate reads to a specific
> DRAM bank (Bank partitioned).This test is running on cpu0 of 4 cpu
> arm_detailed running at 1GHZ frequency with 1MB shared L2 cache and  single
> channel LPDDR3 x32 DRAM. The bank used by cpu0 is not shared between other
> cpu's.
>
>  Test statistics:
>
> system.mem_ctrls.avgQLat
>43816.35   # Average queueing delay per
> DRAM burst
> system.mem_ctrls.avgBusLat
> 5000.00   # Average bus latency per DRAM burst
> system.mem_ctrls.avgMemAccLat
> 63816.35   # Average memory access latency per DRAM
> burst
> system.mem_ctrls.avgRdQLen
> 2.00   # Average read queue length when enqueuing
> system.mem_ctrls.avgGap
> 136814.25   # Average gap between requests
> system.l2.ReadReq_avg_miss_latency::switch_cpus0.data
> 114767.654811   # average ReadReq miss latency
>
>  Based on above test statistics:
>
>  avgMemAccLat is 63ns, which i presume the sum of tRP(15ns)+tRCD(15ns)
> +tCL(15ns)+static latency(20ns).
> Is this breakup correct?
>
>  However the l2.ReadReq_avg_miss_atency is 114ns which is ~50 ns more
> than the avgMemAccLat. I couldn't figure out the components contributing to
> this 50ns latency. Your thoughts on this is much appreciated.
>
>  Regards,
>  Prathap
>
>
>
>
> On Thu, Nov 6, 2014 at 3:03 AM, Andreas Hansson 
> wrote:
>
>>  Hi Prathap,
>>
>>  The avgMemAccLat does indeed include any queueing latency. For the
>> precise components included in the various latencies I would suggest
>> checking the source code.
>>
>>  Note that the controller is not just accounting for the static (and
>> dynamic) DRAM latency, but also the static controller pipeline latency (and
>> dynamic queueing latency). The controller static latency is two parameters
>> that are by default also adding a few 10’s of nanoseconds.
>>
>>  Let me know if you need more help breaking out the various components.
>>
>>  Andreas
>>
>>   From: Prathap Kolakkampadath via gem5-users 
>> Reply-To: Prathap Kolakkampadath , gem5 users
>> mailing list 
>> Date: Wednesday, 5 November 2014 05:36
>> To: Tao Zhang , gem5 users mailing list <
>> gem5-users@gem5.org>, Amin Farmahini 
>> Subject: Re: [gem5-users] DRAM memory access latency
>>
>>  Hi Tao,Amin,
>>
>>  According to gem5 source, MemAccLat is the time difference between the
>> packet enters in the controller and packet leaves the controller. I presume
>>  this added with BusLatency and static backend latency should match with
>> system.l2.ReadReq_avg_miss_latency. However i see a difference of approx
>> 50ns.
>>
>>
>>  As mentioned above if MemAccLat is the time a packet spends in memory
>> controller, then it should include the queuing latency too. In that case
>> the value of  avgQLat looks suspicious. Is the avgQlat part of
>> avgMemAccLat?
>>
>>  Thanks,
>> Prathap
>>
>>
>>
>> On Tue, Nov 4, 2014 at 3:11 PM, Tao Zhang 
>> wrote:
>>
>>>  From the stats, I'd like to use system.mem_ctrls.avgMemAccLat as the
>>> overall average memory latency. It is 63.816ns, which is very close to 60ns
>>> as you calculated. I guess the extra 3.816ns is due to the refresh penalty.
>>>
>>> -Tao
>>>
>>> On Tue, Nov 4, 2014 at 12:10 PM, Prathap Kolakkampadath <
>>> kvprat...@gmail.com> wrote:
>>>
  Hi Toa, Amin,


  Thanks for your reply.

  To discard interbank interference and queueing delay, i have
 partitioned the banks so that the latency benchmark has exclusive access to
 a bank

Re: [gem5-users] modeling L3 last level cache in gem5

[Seyedhamidreza Motaman via gem5-users]

Hello Prateek,

I have the same issue for adding L3 cache. Would you please let me know
what was the if-else ladder you fixed in the code. I would really
appreciate if you send me the cacheconfig.py file . I am getting this error
when I am running gem5

  File "", line 1, in 
  File "/home/mot/gem5/src/python/m5/main.py", line 388, in main
exec filecode in scope
  File "configs/example/fs.py", line 55, in 
import CacheConfig
  File "/home/mot/gem5/configs/common/CacheConfig.py", line 65
if options.l3cache:


On Tue, Apr 8, 2014 at 3:54 AM, Prateek Gupta  wrote:

> Thanks Andreas,
>
> I figured out my mistake in the CacheConfig.py file-a minor bug in the
> if-else ladder. I am now bit stuck in moving further in modeling and
> changing the technology parameters of L3 cache. Please correct me if I am
> wrong as I figured out that the changes are to be made in the
> simpleDRAM.py, cache_impl.hh, simple_dram.hh/cc files for changing the DRAM
> technology parameters but I am not sure, whether by only changing the
> parameters in these files will lend up in modeling the L3 cache as e-DRAM
> or STT-RAM. Kindly let me know what are the additions and in what source
> files are to be done (if possible) and also whether the default
> configuration of the L1, L2 , L3 caches is a typical 6T-SRAM and whether is
> it different from the main memory configuration and how I can change it?
> The command --mem-type="" is used to specify the type for main memory
> only, am I right??
>
>
> Thanks,
> Prateek
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] how to update m5struct in vmlinux_2.6.27-gcc_4.3.4

[Anthony Gutierrez via gem5-users]

These patches will give an idea, and they're not difficult to port.

http://repo.gem5.org/linux-patches/


Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier

On Thu, Nov 6, 2014 at 3:38 PM, Sanem Arslan via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I want to update m5struct.c to take additional information from the
> kernel. I am using kernel, PAL code and disk image for the ALPHA provided
> by UT Texas (http://www.cs.utexas.edu/~parsec_m5/). In order to update
> m5struct, I should reach to files inside vmlinux_2.6.27-gcc_4.3.4 and
> re-compile it. But I dont know how I can do that. Is there anyone who can
> guide me on that issue?
>
> Thanks in advance.
> Sanem.
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] how to update m5struct in vmlinux_2.6.27-gcc_4.3.4

[Sanem Arslan via gem5-users]

Hello,

I want to update m5struct.c to take additional information from the  
kernel. I am using kernel, PAL code and disk image for the ALPHA  
provided by UT Texas (http://www.cs.utexas.edu/~parsec_m5/). In order  
to update m5struct, I should reach to files inside  
vmlinux_2.6.27-gcc_4.3.4 and re-compile it. But I dont know how I can  
do that. Is there anyone who can guide me on that issue?


Thanks in advance.
Sanem.
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] [Gem5 Minor CPU] About the actual "execution" of an instruction

[Mitch Hayenga via gem5-users]

In general there are 3 functions that the CPU calls on instructions in
order to execute them.  These are all functions within the "StaticInst"
class.

1) initiateAcc
2) completeAcc
3) execute

The first 2 are used for memory operations while the 3rd is what you care
about for your integer example.  Look at src/cpu/minor/execute.cc:938

That call to staticInst->execute() will call a generated function that
actually does the add.  This has to deal with how gem5 runs generic ISAs on
multiple CPUs.  The actual function that reads values and adds them
together is located within the ISA description files somewhere under
src/arch/. Depending on the ISA and actual instruction.



On Thu, Nov 6, 2014 at 2:01 PM, Wei Miao via gem5-users  wrote:

> Hello:
>
> I am now using Gem5 to do some simulation and design on CPU. I am now
> looking at the minor CPU model. However, I cannot find where the
> instruction will be truly "executed". For example, if I have a add
> instruction, where will the "add" itself happened? I try to find it in
> /src/cpu/minor/execute.cc and  /src/cpu/minor/func_unit.cc but I cannot
> find it. I will appreciate any ideas and helps.
>
> Thank you very much!
>
> Wei Miao
> 11/6/2014
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] DRAM memory access latency

[Andreas Hansson via gem5-users]

Hi Prathap,

I suspect the answer to the mysterious 50 ns is due to the responses being sent 
back using a so called “queued port” in gem5. Thus, from the memory 
controller’s point of view the packet is all done, but is now waiting in the 
port until the crossbar can accept it. This queue can hold a number of packets 
if there has been a burst of responses that are trickling through the crossbar 
on their way back.

You can always run with some debug flags to verify this (XBar, DRAM, 
PacketQueue etc).

Coincidentally I have been working on a patch to remove this “invisible” queue 
and should hopefully have this on the review board shortly.

Andreas

From: Prathap Kolakkampadath mailto:kvprat...@gmail.com>>
Date: Thursday, November 6, 2014 at 5:47 PM
To: Andreas Hansson mailto:andreas.hans...@arm.com>>
Cc: gem5 users mailing list mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] DRAM memory access latency

Hello Andreas,

Thanks for your reply.


Ok. I got that the memory access latency indeed includes the queueing latency. 
And for the read/write request that miss the buffer has a static latency of  
Static frontend latency + Static backend latency.


To summarize, the test i run is a latency benchmark which is a pointer chasing 
test(only one request at a time) , generate reads to a specific DRAM bank (Bank 
partitioned).This test is running on cpu0 of 4 cpu arm_detailed running at 1GHZ 
frequency with 1MB shared L2 cache and  single channel LPDDR3 x32 DRAM. The 
bank used by cpu0 is not shared between other cpu's.

Test statistics:

system.mem_ctrls.avgQLat
   43816.35   # Average queueing delay per DRAM 
burst
system.mem_ctrls.avgBusLat5000.00   # 
Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat63816.35   # 
Average memory access latency per DRAM burst
system.mem_ctrls.avgRdQLen   2.00   # 
Average read queue length when enqueuing
system.mem_ctrls.avgGap 136814.25   # 
Average gap between requests
system.l2.ReadReq_avg_miss_latency::switch_cpus0.data 114767.654811 
  # average ReadReq miss latency

Based on above test statistics:

avgMemAccLat is 63ns, which i presume the sum of tRP(15ns)+tRCD(15ns) 
+tCL(15ns)+static latency(20ns).
Is this breakup correct?

However the l2.ReadReq_avg_miss_atency is 114ns which is ~50 ns more than the 
avgMemAccLat. I couldn't figure out the components contributing to this 50ns 
latency. Your thoughts on this is much appreciated.

Regards,
Prathap




On Thu, Nov 6, 2014 at 3:03 AM, Andreas Hansson 
mailto:andreas.hans...@arm.com>> wrote:
Hi Prathap,

The avgMemAccLat does indeed include any queueing latency. For the precise 
components included in the various latencies I would suggest checking the 
source code.

Note that the controller is not just accounting for the static (and dynamic) 
DRAM latency, but also the static controller pipeline latency (and dynamic 
queueing latency). The controller static latency is two parameters that are by 
default also adding a few 10’s of nanoseconds.

Let me know if you need more help breaking out the various components.

Andreas

From: Prathap Kolakkampadath via gem5-users 
mailto:gem5-users@gem5.org>>
Reply-To: Prathap Kolakkampadath 
mailto:kvprat...@gmail.com>>, gem5 users mailing list 
mailto:gem5-users@gem5.org>>
Date: Wednesday, 5 November 2014 05:36
To: Tao Zhang mailto:tao.zhang.0...@gmail.com>>, gem5 
users mailing list mailto:gem5-users@gem5.org>>, Amin 
Farmahini mailto:amin...@gmail.com>>
Subject: Re: [gem5-users] DRAM memory access latency

Hi Tao,Amin,

According to gem5 source, MemAccLat is the time difference between the packet 
enters in the controller and packet leaves the controller. I presume  this 
added with BusLatency and static backend latency should match with  
system.l2.ReadReq_avg_miss_latency. However i see a difference of approx 50ns.


As mentioned above if MemAccLat is the time a packet spends in memory 
controller, then it should include the queuing latency too. In that case the 
value of  avgQLat looks suspicious. Is the avgQlat part of avgMemAccLat?

Thanks,
Prathap



On Tue, Nov 4, 2014 at 3:11 PM, Tao Zhang 
mailto:tao.zhang.0...@gmail.com>> wrote:
>From the stats, I'd like to use system.mem_ctrls.avgMemAccLat as the overall 
>average memory latency. It is 63.816ns, which is very close to 60ns as you 
>calculated. I guess the extra 3.816ns is due to the refresh penalty.

-Tao

On Tue, Nov 4, 2014 at 12:10 PM, Prathap Kolakkampadath 
mailto:kvprat...@gmail.com>> wrote:
Hi Toa, Amin,


Thanks for your reply.

To discard interbank interference and queueing delay, i have partitioned the 
banks so that the latency benchmark has exclusive access to a bank. Also 
latency benchmark is a pointer chasing benchmark, which will generate a single 
read request at a time.


stats

[gem5-users] [Gem5 Minor CPU] About the actual "execution" of an instruction

[Wei Miao via gem5-users]

Hello:

I am now using Gem5 to do some simulation and design on CPU. I am now
looking at the minor CPU model. However, I cannot find where the
instruction will be truly "executed". For example, if I have a add
instruction, where will the "add" itself happened? I try to find it in
/src/cpu/minor/execute.cc and  /src/cpu/minor/func_unit.cc but I cannot
find it. I will appreciate any ideas and helps.

Thank you very much!

Wei Miao
11/6/2014
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] DRAM memory access latency

[Prathap Kolakkampadath via gem5-users]

Hello Andreas,

Thanks for your reply.


Ok. I got that the memory access latency indeed includes the queueing
latency. And for the read/write request that miss the buffer has a static
latency of  Static frontend latency + Static backend latency.


To summarize, the test i run is a latency benchmark which is a pointer
chasing test(only one request at a time) , generate reads to a specific
DRAM bank (Bank partitioned).This test is running on cpu0 of 4 cpu
arm_detailed running at 1GHZ frequency with 1MB shared L2 cache and  single
channel LPDDR3 x32 DRAM. The bank used by cpu0 is not shared between other
cpu's.

Test statistics:

system.mem_ctrls.avgQLat
   43816.35   # Average queueing delay per
DRAM burst
system.mem_ctrls.avgBusLat5000.00
# Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat63816.35
# Average memory access latency per DRAM burst
system.mem_ctrls.avgRdQLen   2.00
# Average read queue length when enqueuing
system.mem_ctrls.avgGap 136814.25
# Average gap between requests
system.l2.ReadReq_avg_miss_latency::switch_cpus0.data
114767.654811   # average ReadReq miss latency

Based on above test statistics:

avgMemAccLat is 63ns, which i presume the sum of tRP(15ns)+tRCD(15ns)
+tCL(15ns)+static latency(20ns).
Is this breakup correct?

However the l2.ReadReq_avg_miss_atency is 114ns which is ~50 ns more than
the avgMemAccLat. I couldn't figure out the components contributing to this
50ns latency. Your thoughts on this is much appreciated.

Regards,
Prathap




On Thu, Nov 6, 2014 at 3:03 AM, Andreas Hansson 
wrote:

>  Hi Prathap,
>
>  The avgMemAccLat does indeed include any queueing latency. For the
> precise components included in the various latencies I would suggest
> checking the source code.
>
>  Note that the controller is not just accounting for the static (and
> dynamic) DRAM latency, but also the static controller pipeline latency (and
> dynamic queueing latency). The controller static latency is two parameters
> that are by default also adding a few 10’s of nanoseconds.
>
>  Let me know if you need more help breaking out the various components.
>
>  Andreas
>
>   From: Prathap Kolakkampadath via gem5-users 
> Reply-To: Prathap Kolakkampadath , gem5 users
> mailing list 
> Date: Wednesday, 5 November 2014 05:36
> To: Tao Zhang , gem5 users mailing list <
> gem5-users@gem5.org>, Amin Farmahini 
> Subject: Re: [gem5-users] DRAM memory access latency
>
>  Hi Tao,Amin,
>
>  According to gem5 source, MemAccLat is the time difference between the
> packet enters in the controller and packet leaves the controller. I presume
>  this added with BusLatency and static backend latency should match with
> system.l2.ReadReq_avg_miss_latency. However i see a difference of approx
> 50ns.
>
>
>  As mentioned above if MemAccLat is the time a packet spends in memory
> controller, then it should include the queuing latency too. In that case
> the value of  avgQLat looks suspicious. Is the avgQlat part of
> avgMemAccLat?
>
>  Thanks,
> Prathap
>
>
>
> On Tue, Nov 4, 2014 at 3:11 PM, Tao Zhang 
> wrote:
>
>>  From the stats, I'd like to use system.mem_ctrls.avgMemAccLat as the
>> overall average memory latency. It is 63.816ns, which is very close to 60ns
>> as you calculated. I guess the extra 3.816ns is due to the refresh penalty.
>>
>> -Tao
>>
>> On Tue, Nov 4, 2014 at 12:10 PM, Prathap Kolakkampadath <
>> kvprat...@gmail.com> wrote:
>>
>>>  Hi Toa, Amin,
>>>
>>>
>>>  Thanks for your reply.
>>>
>>>  To discard interbank interference and queueing delay, i have
>>> partitioned the banks so that the latency benchmark has exclusive access to
>>> a bank. Also latency benchmark is a pointer chasing benchmark, which will
>>> generate a single read request at a time.
>>>
>>>
>>>  stats.txt says this:
>>>
>>> system.mem_ctrls.avgQLat
>>> 43816.35   # Average queueing delay per DRAM burst
>>> system.mem_ctrls.avgBusLat
>>> 5000.00   # Average bus latency per DRAM burst
>>> system.mem_ctrls.avgMemAccLat
>>> 63816.35   # Average memory access latency per DRAM
>>> burst
>>> system.mem_ctrls.avgRdQLen
>>> 2.00   # Average read queue length when enqueuing
>>> system.mem_ctrls.avgGap
>>> 136814.25   # Average gap between requests
>>> system.l2.ReadReq_avg_miss_latency::switch_cpus0.data
>>> 114767.654811   # average ReadReq miss latency
>>>
>>>  The average Gap between requests is equal to the L2 latency + DRAM
>>> Latency for this test. Also avgRdQLen is 2 because cache line size is 64
>>> and DRAM interface is x32.
>>>
>>>  Is the final latency sum of avgQLat + avgBusLat + avgMemAccLat ?
>>> Also when avgRdQLen is 2, i am not sure what amounts to high queueing
>>> latency?
>>>
>>>  Regards,
>>>  Prathap
>>>
>>>
>>>
>>> On Tue, Nov 4, 2014 at 1:38 PM, Amin Farmahini 

[gem5-users] file modification

[babak aghaei via gem5-users]

Hi What we would do when we modified a file in gem5 repo for seeing the result 
of this modification!?  
---Babak Aghaei 
Ph.D candidate


  ___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

[babak aghaei via gem5-users]

Hi What we would do when we modified a file in gem5 repo for seeing the result 
of this modification!?  
---Babak Aghaei 
Ph.D candidate
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Simulation core of gem5

[Andreas Hansson via gem5-users]

Hi Fela,

Could you perhaps re-state your question? (and please be concise :-)

gem5 includes a fairly Œnormal¹ text-book example of a discrete-event
simulation kernel.

If you think there are specific aspects that are important, then could you
perhaps take a first stab at a page explaining the key aspects?

Thanks,

Andreas

On 06/11/2014 11:06, "fela via gem5-users"  wrote:

>
>>
>>
>> Thank you steve but it unfortunatly doen't respond my question.
>
>I contacted some users of gem5 but no one has a response to my question.
>Every body is interested in what he can model with gem5 and not the
>simulation core of Gem5 but I think it is the first thing that one has to
>understand before implementing his own model!
>what are the time and execution models in gem5? How much eventQueues are
>in
>this simulator? Who choose the next event to serve? So many questions!!
>This is important for me because I wanted to study distributed and
>parallelized simulations using gem5.
>Due to the lack of documentation for gem5, I started studying OMNET++ and
>SST which are well documented.
>Gem5 seems to be un good and promising platform, I suggest to add a page
>to
>gem5 site explaining this important aspect of the simulator for the futur
>users.
>
>Thanks to all,
>
>Fela,
>PhD student.
>
>
>>
>>
>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users  gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>
>
>
>___
>gem5-users mailing list
>gem5-users@gem5.org
>http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>


-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium.  Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No:  2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England & Wales, Company No:  2548782

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] L2 Cache size in fullsystem

[Ahmad Hassan via gem5-users]

Matheus,

Booting kernel shows fake cache sizes. If you want to see what cache sizes
are configured, then put a print statement in
src/mem/cache/base.cc:BaseCache::BaseCache(const Params *p)

Regards
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] L2 Cache size in fullsystem

[Matheus Alcântara Souza via gem5-users]

Hi,

I wonder if, when we run a x86 fullsystem simulation, the values printed
out by the console can be "discarded".

That is, if I start a simulation using for example 8 cores, with 256kB of
L2 Cache Size, I keep retrieving this:

###
Booting processor 9 APIC 0x9 ip 0x6000
Initializing CPU#0
Calibrating delay loop (skipped) preset value.. 3999.96 BogoMIPS
(lpj=723)
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
#3

It is normal being the L2 Cache size 1024K? I'm doing something wrong?
If i change the size, it keeps 1024K, but the results change.

Best regards,
Matheus

--
Atenciosamente,
Matheus Alcântara Souza
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Query regarding the sim_seconds field in stats.txt

[Matheus Alcântara Souza via gem5-users]

Hello

Q1) What does sim_seconds denote. Isn't it the time elapsed between start
and end of the simulation
R: sim_seconds denotes how much time your enviroment should be running if
it was a real enviroment. If you want to know how much time you simulation
was running, that is, how many time gem5 spent, check host_seconds.

Q2) Does the figures in stats.txt represent the numbers obtained for entire
system simuation, or is it just the numbers obtained for the benchmark
which is running in the system which is being simulated.
R: You can use the '/sbin/m5 resetstats' to start a new data collect during
the simulation or '/sbin/m5 dumpstats' to write the current stats to a
section in stats.txt (the sections will be separated throug '---Begin
Simulation... ---', and '--- End Simulation ...---' lines). You can
instrumentate your code also. Take a look at http://www.m5sim.org/M5ops

Best regards
Matheus

2014-11-06 8:43 GMT-02:00 rahul shrivastava via gem5-users <
gem5-users@gem5.org>:

> Hi,
>
> I am running a ARM architecture full system simulation mode. I kept the
> system as it is for around one hour and didnt run any benchmark. After
> this, I checked the stats.txt file for number of seconds elapsed in
> simulation(sim_seconds), and it showed the value 40 seconds.
> Could you please let me know the following -
>
> Q1) What does sim_seconds denote. Isn't it the time elapsed between start
> and end of the simulation
> Q2) Does the figures in stats.txt represent the numbers obtained for
> entire system simuation, or is it just the numbers obtained for the
> benchmark which is running in the system which is being simulated.
>
>
> Regards
> Rahul
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>



-- 

--
Atenciosamente,
Matheus Alcântara Souza
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Simulation core of gem5

[fela via gem5-users]

> 
> 
> Thank you steve but it unfortunatly doen't respond my question.

I contacted some users of gem5 but no one has a response to my question.
Every body is interested in what he can model with gem5 and not the
simulation core of Gem5 but I think it is the first thing that one has to
understand before implementing his own model!
what are the time and execution models in gem5? How much eventQueues are in
this simulator? Who choose the next event to serve? So many questions!!
This is important for me because I wanted to study distributed and
parallelized simulations using gem5.
Due to the lack of documentation for gem5, I started studying OMNET++ and
SST which are well documented. 
Gem5 seems to be un good and promising platform, I suggest to add a page to
gem5 site explaining this important aspect of the simulator for the futur users.

Thanks to all,

Fela,
PhD student.


> 
> 
> 
> 
> ___
> gem5-users mailing list
> gem5-users  gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users




___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Query regarding the sim_seconds field in stats.txt

[rahul shrivastava via gem5-users]

Hi,

I am running a ARM architecture full system simulation mode. I kept the
system as it is for around one hour and didnt run any benchmark. After
this, I checked the stats.txt file for number of seconds elapsed in
simulation(sim_seconds), and it showed the value 40 seconds.
Could you please let me know the following -

Q1) What does sim_seconds denote. Isn't it the time elapsed between start
and end of the simulation
Q2) Does the figures in stats.txt represent the numbers obtained for entire
system simuation, or is it just the numbers obtained for the benchmark
which is running in the system which is being simulated.


Regards
Rahul
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] DRAM memory access latency

[Andreas Hansson via gem5-users]

Hi Prathap,

The avgMemAccLat does indeed include any queueing latency. For the precise 
components included in the various latencies I would suggest checking the 
source code.

Note that the controller is not just accounting for the static (and dynamic) 
DRAM latency, but also the static controller pipeline latency (and dynamic 
queueing latency). The controller static latency is two parameters that are by 
default also adding a few 10’s of nanoseconds.

Let me know if you need more help breaking out the various components.

Andreas

From: Prathap Kolakkampadath via gem5-users 
mailto:gem5-users@gem5.org>>
Reply-To: Prathap Kolakkampadath 
mailto:kvprat...@gmail.com>>, gem5 users mailing list 
mailto:gem5-users@gem5.org>>
Date: Wednesday, 5 November 2014 05:36
To: Tao Zhang mailto:tao.zhang.0...@gmail.com>>, gem5 
users mailing list mailto:gem5-users@gem5.org>>, Amin 
Farmahini mailto:amin...@gmail.com>>
Subject: Re: [gem5-users] DRAM memory access latency

Hi Tao,Amin,

According to gem5 source, MemAccLat is the time difference between the packet 
enters in the controller and packet leaves the controller. I presume  this 
added with BusLatency and static backend latency should match with  
system.l2.ReadReq_avg_miss_latency. However i see a difference of approx 50ns.


As mentioned above if MemAccLat is the time a packet spends in memory 
controller, then it should include the queuing latency too. In that case the 
value of  avgQLat looks suspicious. Is the avgQlat part of avgMemAccLat?

Thanks,
Prathap



On Tue, Nov 4, 2014 at 3:11 PM, Tao Zhang 
mailto:tao.zhang.0...@gmail.com>> wrote:
>From the stats, I'd like to use system.mem_ctrls.avgMemAccLat as the overall 
>average memory latency. It is 63.816ns, which is very close to 60ns as you 
>calculated. I guess the extra 3.816ns is due to the refresh penalty.

-Tao

On Tue, Nov 4, 2014 at 12:10 PM, Prathap Kolakkampadath 
mailto:kvprat...@gmail.com>> wrote:
Hi Toa, Amin,


Thanks for your reply.

To discard interbank interference and queueing delay, i have partitioned the 
banks so that the latency benchmark has exclusive access to a bank. Also 
latency benchmark is a pointer chasing benchmark, which will generate a single 
read request at a time.


stats.txt says this:

system.mem_ctrls.avgQLat 43816.35   # 
Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat5000.00   # 
Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat63816.35   # 
Average memory access latency per DRAM burst
system.mem_ctrls.avgRdQLen   2.00   # 
Average read queue length when enqueuing
system.mem_ctrls.avgGap 136814.25   # 
Average gap between requests
system.l2.ReadReq_avg_miss_latency::switch_cpus0.data 114767.654811 
  # average ReadReq miss latency

The average Gap between requests is equal to the L2 latency + DRAM Latency for 
this test. Also avgRdQLen is 2 because cache line size is 64 and DRAM interface 
is x32.

Is the final latency sum of avgQLat + avgBusLat + avgMemAccLat ?
Also when avgRdQLen is 2, i am not sure what amounts to high queueing latency?

Regards,
Prathap



On Tue, Nov 4, 2014 at 1:38 PM, Amin Farmahini 
mailto:amin...@gmail.com>> wrote:
Prathap,

You are probably missing DRAM queuing latency (major reason) and other on-chip 
latencies (such as bus latency) if any.

Thanks,
Amin

On Tue, Nov 4, 2014 at 1:28 PM, Prathap Kolakkampadath via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hello Users,

I am measuring DRAM worst case memory access latency(tRP+tRCD +tCL+tBURST) 
using a latency benchmark on arm_detailed(1Ghz) with 1MB shared L2 cache and  
LPDDR3 x32 DRAM.

According to DRAM timing parameters, tRP = '15ns, tRCD = '15ns', tCL = '15ns', 
tBURST = '5ns'. Latency measured by the benchmark on cache hit is 22 ns and on 
cache miss is  132ns. Which means DRAM memory access latency ~ 110ns. However 
according to calculation it should  be 
tRP+tRCD+tCL+tBurst+static_backend_latency(10ns) = 60ns.


The latency what i observe is almost 50ns higher than what it is supposed to 
be. Is there anything which I am missing? Do any one know what else could add 
to the DRAM memory access latency?

Thanks,
Prathap


___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users





-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No: 25