Re: [gem5-users] Printing Statistics type variable using DPRINTF for debugging

[Arun Subramaniyan via gem5-users]

Thank you for the suggestions.

Regards,
Arun

On Thu, Nov 6, 2014 at 3:18 AM, Patrick  wrote:

> Arun,
>
> I haven't working directly with the Formula class, but I looked over the
> files in which it is defined (src/base/statistics.hh and
> src/base/statistics.cc). Note that the class is defined in the header file
> as:  "A formula for statistics that is calculated when printed. A formula
> is stored as a tree of Nodes that represent the equation to calculate." So
> this is a non-trivial object. Glancing at it, it does have a member
> function named "str" that appears that it will print out the tree, which me
> be helpful for you. There is also a function called "result" that returns
> the "result of the formula" in a VResult type.
>
> I hope this will help you at least to get started on the right path.
>
> -Patrick La Fratta
>
> On Tue, Nov 4, 2014 at 7:50 AM, Arun Subramaniyan via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hello everyone
>>
>> I am trying to monitor how a particular Stats::Formula type variable
>> (like cache miss rate) evolves at runtime. I have tried to display its
>> value using DPRINTF but to no avail. Can someone guide me on how to
>> accomplish this?
>>
>> Thank you.
>>
>> Regards,
>> Arun
>>
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>
>


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[gem5-users] Purpose of Latency in prefetcher

[DizzyJoe via gem5-users]

Hi,

I am working on a prefetcher in gem5 and came across a flag called
'latency', which seems to be hard coded to 1 (cycles?) in Prefetcher.py
and this latency is added every time a prefetch request is issued by the
base prefetcher, I wanted to know the impact of this and the reason for
fixing this at 10k?





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[gem5-users] Average latency

[Matheus Alcântara Souza via gem5-users]

Hello!

Is this value in picoseconds?

system.ruby.network.average_latency 34.061524


Thank you.

--
Atenciosamente,
Matheus Alcântara Souza
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Re: [gem5-users] Adding L3 cache

[Andreas Hansson via gem5-users]

Hi Hamid,

The control flow here is very unfortunate to say the least. What happens if 
there is an l3 but no l2 etc?

The only thing that stands out is:

system.cpu[i].connectAllPorts(system.tol3bus, system.membus)

This is definitely not right.

I’d suggest to check the config.dot (.pdf and .svg) in the m5out directory for 
a visual representation of the system you have created. That should hopefully 
help in getting it right.

Andreas

From: Seyedhamidreza Motaman via gem5-users 
mailto:gem5-users@gem5.org>>
Reply-To: Seyedhamidreza Motaman 
mailto:mota...@mail.usf.edu>>, gem5 users mailing list 
mailto:gem5-users@gem5.org>>
Date: Tuesday, November 11, 2014 at 11:42 PM
To: gem5 users mailing list mailto:gem5-users@gem5.org>>
Subject: [gem5-users] Adding L3 cache


Hello All,

I would really appreciate if someone answer my question. I really need to solve 
this problem .

Best regards,
Hamid



I am trying to add l3 cache to gem5 cache hierarchy.
I modified the option.py by simply adding:
parser.add_option("--l3cache", action="store_true")

and I modified cacheconfig.py as below (highlighted in red )

def config_cache(options, system):
if options.cpu_type == "arm_detailed":
try:
from O3_ARM_v7a import *
except:
print "arm_detailed is unavailable. Did you compile the O3 model?"
sys.exit(1)

dcache_class, icache_class, l2_cache_class, l3_cache_class = \
O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, O3_ARM_v7aL3
else:
dcache_class, icache_class, l2_cache_class, l3_cache_class = \
L1Cache, L1Cache, L2Cache, L3Cache

# Set the cache line size of the system
system.cache_line_size = options.cacheline_size

if options.l3cache:
system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
   size=options.l3_size,
   assoc=options.l3_assoc)

system.tol3bus = CoherentBus(clk_domain = system.cpu_clk_domain,
 width = 32)
system.l3.cpu_side = system.tol3bus.master
system.l3.mem_side = system.membus.slave
elif options.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs, and set the L1-to-L2 bus width to 32
# bytes (256 bits).
system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
   size=options.l2_size,
   assoc=options.l2_assoc)

system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
 width = 32)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave

for i in xrange(options.num_cpus):
if options.caches:
icache = icache_class(size=options.l1i_size,
  assoc=options.l1i_assoc)
dcache = dcache_class(size=options.l1d_size,
  assoc=options.l1d_assoc)



# When connecting the caches, the clock is also inherited
# from the CPU in question
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
  PageTableWalkerCache(),
  PageTableWalkerCache())
else:
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
if options.l3cache:
system.cpu[i].l2 = 
l2_cache_class(clk_domain=system.cpu_clk_domain,
   size=options.l2_size,
   assoc=options.l2_assoc)
system.cpu[i].tol2bus = CoherentBus(clk_domain = 
system.cpu_clk_domain,
 width = 32)
system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.master
system.cpu[i].l2.mem_side = system.tol3bus.slave
system.cpu[i].createInterruptController()
if options.l3cache:
system.cpu[i].connectAllPorts(system.tol3bus, system.membus)

elif options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)


else:
system.cpu[i].connectAllPorts(system.membus)

return system

---
when I am simulating i am getting this error:
Listening for system connection on port 3456
  0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
warn: CoherentBus system.cpu0.tol2bus has no snooping ports attached!
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
warn: CoherentBus system.cpu1.tol2bus has no snooping po

Re: [gem5-users] Adding L3 cache

[Kumail Ahmed via gem5-users]

Hello Hamid,

Can you paste the command line option that you typed? Are you using FS mode
or SE mode?

Regards,
Kumail Ahmed
TU Kaiserslautern, Germany

On Wed, Nov 12, 2014 at 12:42 AM, Seyedhamidreza Motaman via gem5-users <
gem5-users@gem5.org> wrote:

>
> Hello All,
>
> I would really appreciate if someone answer my question. I really need to
> solve this problem .
>
> Best regards,
> Hamid
>
>
>
> I am trying to add l3 cache to gem5 cache hierarchy.
> I modified the option.py by simply adding:
> parser.add_option("--l3cache", action="store_true")
>
> and I modified cacheconfig.py as below (highlighted in red )
>
> def config_cache(options, system):
> if options.cpu_type == "arm_detailed":
> try:
> from O3_ARM_v7a import *
> except:
> print "arm_detailed is unavailable. Did you compile the O3
> model?"
> sys.exit(1)
>
> dcache_class, icache_class, l2_cache_class, l3_cache_class = \
> O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2,
> O3_ARM_v7aL3
> else:
> dcache_class, icache_class, l2_cache_class, l3_cache_class = \
> L1Cache, L1Cache, L2Cache, L3Cache
>
> # Set the cache line size of the system
> system.cache_line_size = options.cacheline_size
>
> if options.l3cache:
> system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
>size=options.l3_size,
>assoc=options.l3_assoc)
>
> system.tol3bus = CoherentBus(clk_domain = system.cpu_clk_domain,
>  width = 32)
> system.l3.cpu_side = system.tol3bus.master
> system.l3.mem_side = system.membus.slave
> elif options.l2cache:
> # Provide a clock for the L2 and the L1-to-L2 bus here as they
> # are not connected using addTwoLevelCacheHierarchy. Use the
> # same clock as the CPUs, and set the L1-to-L2 bus width to 32
> # bytes (256 bits).
> system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
>size=options.l2_size,
>assoc=options.l2_assoc)
>
> system.tol2bus = CoherentBus(clk_domain =
> system.cpu_clk_domain,
>  width = 32)
> system.l2.cpu_side = system.tol2bus.master
> system.l2.mem_side = system.membus.slave
>
> for i in xrange(options.num_cpus):
> if options.caches:
> icache = icache_class(size=options.l1i_size,
>   assoc=options.l1i_assoc)
> dcache = dcache_class(size=options.l1d_size,
>   assoc=options.l1d_assoc)
>
>
>
> # When connecting the caches, the clock is also inherited
> # from the CPU in question
> if buildEnv['TARGET_ISA'] == 'x86':
> system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
>
> PageTableWalkerCache(),
>
> PageTableWalkerCache())
> else:
> system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
> if options.l3cache:
> system.cpu[i].l2 =
> l2_cache_class(clk_domain=system.cpu_clk_domain,
>size=options.l2_size,
>assoc=options.l2_assoc)
> system.cpu[i].tol2bus = CoherentBus(clk_domain =
> system.cpu_clk_domain,
>  width = 32)
> system.cpu[i].l2.cpu_side =
> system.cpu[i].tol2bus.master
> system.cpu[i].l2.mem_side = system.tol3bus.slave
> system.cpu[i].createInterruptController()
> if options.l3cache:
> system.cpu[i].connectAllPorts(system.tol3bus, system.membus)
>
> elif options.l2cache:
> system.cpu[i].connectAllPorts(system.tol2bus,
> system.membus)
>
>
> else:
> system.cpu[i].connectAllPorts(system.membus)
>
> return system
>
> ---
> when I am simulating i am getting this error:
> Listening for system connection on port 3456
>   0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00
> 2009
> 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
> warn: CoherentBus system.cpu0.tol2bus has no snooping ports attached!
> 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
> warn: CoherentBus system.cpu1.tol2bus has no snooping ports attached!
> 0: system.remote_gdb.listener: listening for remote gdb #2 on port 7002
> warn: CoherentBus system.cpu2.tol2bus has no snooping ports attached!
> 0: system.remote_gdb.listener: listening for remote gdb #3 on port 7003
> warn: CoherentBus system.cpu3.tol2bus has no snooping ports attached!
> gem5.opt: build/ALPHA/base/statistics.hh:1216: Derived&
> Stats::Vector2dBase::init(Stats::size_type,
> Stats::size_type) [with 

[gem5-users] Adding L3 cache

[Seyedhamidreza Motaman via gem5-users]

Hello All,

I would really appreciate if someone answer my question. I really need to
solve this problem .

Best regards,
Hamid



I am trying to add l3 cache to gem5 cache hierarchy.
I modified the option.py by simply adding:
parser.add_option("--l3cache", action="store_true")

and I modified cacheconfig.py as below (highlighted in red )

def config_cache(options, system):
if options.cpu_type == "arm_detailed":
try:
from O3_ARM_v7a import *
except:
print "arm_detailed is unavailable. Did you compile the O3
model?"
sys.exit(1)

dcache_class, icache_class, l2_cache_class, l3_cache_class = \
O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, O3_ARM_v7aL3
else:
dcache_class, icache_class, l2_cache_class, l3_cache_class = \
L1Cache, L1Cache, L2Cache, L3Cache

# Set the cache line size of the system
system.cache_line_size = options.cacheline_size

if options.l3cache:
system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
   size=options.l3_size,
   assoc=options.l3_assoc)

system.tol3bus = CoherentBus(clk_domain = system.cpu_clk_domain,
 width = 32)
system.l3.cpu_side = system.tol3bus.master
system.l3.mem_side = system.membus.slave
elif options.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs, and set the L1-to-L2 bus width to 32
# bytes (256 bits).
system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
   size=options.l2_size,
   assoc=options.l2_assoc)

system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
 width = 32)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave

for i in xrange(options.num_cpus):
if options.caches:
icache = icache_class(size=options.l1i_size,
  assoc=options.l1i_assoc)
dcache = dcache_class(size=options.l1d_size,
  assoc=options.l1d_assoc)



# When connecting the caches, the clock is also inherited
# from the CPU in question
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,

PageTableWalkerCache(),

PageTableWalkerCache())
else:
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
if options.l3cache:
system.cpu[i].l2 =
l2_cache_class(clk_domain=system.cpu_clk_domain,
   size=options.l2_size,
   assoc=options.l2_assoc)
system.cpu[i].tol2bus = CoherentBus(clk_domain =
system.cpu_clk_domain,
 width = 32)
system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.master
system.cpu[i].l2.mem_side = system.tol3bus.slave
system.cpu[i].createInterruptController()
if options.l3cache:
system.cpu[i].connectAllPorts(system.tol3bus, system.membus)

elif options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)


else:
system.cpu[i].connectAllPorts(system.membus)

return system

---
when I am simulating i am getting this error:
Listening for system connection on port 3456
  0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00
2009
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
warn: CoherentBus system.cpu0.tol2bus has no snooping ports attached!
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
warn: CoherentBus system.cpu1.tol2bus has no snooping ports attached!
0: system.remote_gdb.listener: listening for remote gdb #2 on port 7002
warn: CoherentBus system.cpu2.tol2bus has no snooping ports attached!
0: system.remote_gdb.listener: listening for remote gdb #3 on port 7003
warn: CoherentBus system.cpu3.tol2bus has no snooping ports attached!
gem5.opt: build/ALPHA/base/statistics.hh:1216: Derived&
Stats::Vector2dBase::init(Stats::size_type,
Stats::size_type) [with Derived = Stats::Vector2d, Stor = Stats::StatStor,
Stats::size_type = unsigned int]: Assertion `_x > 0 && _y > 0 && "sizes
must be positive!"' failed.

I attached l2 cache for each core to coherent bus but error says that
CoherentBus system.cpu0.tol2bus has no snooping ports attached!
Am I missing something? I would really appreciate if someone point out my
mistake

Regards,
Hamid
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[gem5-users] Different latencies in Ruby

[Rodrigo Reynolds Ramírez via gem5-users]

Hello everyone,

I need to emulate a stt-ram cell using Ruby model. I know how to do it in the 
classic model but I need to use the Ruby model. 

Is it possible to modify the Ruby model for having different read and write 
latencies?

Thanks in advance

Rodrigo
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[gem5-users] Router Statistics

[babak aghaei via gem5-users]

Hello, 
 When We run the simulation with garnet  mode(e.g. 2*2 Mesh topology), We have 
4 router. Why in the stats.txt file We just see one router statistics? I would 
appreciate you if you give some hits. 

Thank you. 
Best
---Babak Aghaei 
Ph.D candidate


   

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Re: [gem5-users] confusing cycle number

[Mitch Hayenga via gem5-users]

numCycles is only incremented on cycles where the CPU is clocked (see
src/cpu/o3/cpu.cc: line 540).

Two things can lead to this not correlating with the number of sim_ticks.
1) Quiesce instructions ("wait for interrupt" on ARM), cause the CPU to
sleep until an interrupt or some external event occurs.
2) If the O3 CPU detects a lack of activity (say stalled for a long time on
an outstanding memory miss and nothing else is occurring in the CPU, it
goes to sleep - this is pretty rare though and usually doesn't last for
many cycles).

Hope that helps.  Basically its just the number of cycles where the CPU was
"clocked", whereas sim_ticks should correlate to wall clock time.

On Tue, Nov 11, 2014 at 4:34 AM, Christian List via gem5-users <
gem5-users@gem5.org> wrote:

> Hello :)
> Ive simulated some parsec benchmarks on an alpha architecture with gem5 on
> a single core (periodically dumping stats).
>
> For the execution I used the parameter --cpu-clock='2GHz'
>
> In the output stat.txt I get the following parameters:
>
> sim_seconds = 0.009517
> sim_ticks = 9517306000
> numCycles = 4540375
>
> I can see here, that sim_seconds dont correlate to numCycles cause:
>
> duration of 1 Cycle = 1 second / 2 * 10^9
> number of Cycles = sim_seconds / duration of 1 cycle
>
> When I do this by hand I get  19034000 for numCycles which is different to
> the output of gem5.
>
> I dont unterstand what I am missing :)
>
> Best regards
> Christian
>
>
>
>
>
>
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Re: [gem5-users] all the cores are not online when performing ARM full system simulation to test DVFS

[Stephan Diestelhorst via gem5-users]

Hi Rahul,

On 11.11.2014 07:20, "rahul shrivastava" 
mailto:rshrivasta...@gmail.com>> wrote:
I am actually using a dtb file only and not dts, Sorry for a typo in my 
previous mail. Please find attached config.ini and config.json file.

Thanks for these.  I think what you need to change is the socket_id for every 
core in your configuration.  For per-core DVFS (and associated DTBs), you need 
to reflect the per-core-ness through putting the cores into single core 
“sockets”.  What that means is that you need to change your configuration and 
change every CPU to have a different socket_id.

You can also try non-per-core DTBs, that should just work with the current 
config.

Thanks,
  Stephan

-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England & Wales, Company No: 2548782
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[gem5-users] Fwd: Sharing L2 cache

[Kumail Ahmed via gem5-users]

Thank you very much andreas :) I did it!

Can you tell me how I can add l3cache in the classical memory model? Do I
have to create a new l3cache class can share it on the l2 bus?

Thanks again,
Kumail Ahmed
Masters Student
TU Kaiserslautern, Germany

On Tue, Nov 11, 2014 at 1:56 PM, Andreas Hansson 
wrote:

>  Hi Kumail,
>
>  The crossbar in gem5 supports address striping, so you can create a
> “toL2Bus” that interleaves between two L2 caches. Have a look at
> config/common/MemConfig.py for how the interleaving is configured (for the
> memory channels). You should be able to do something similar.
>
>  Andreas
>
>   From: Kumail Ahmed via gem5-users 
> Reply-To: Kumail Ahmed , gem5 users mailing list <
> gem5-users@gem5.org>
> Date: Tuesday, 11 November 2014 10:45
> To: "gem5-users@gem5.org" 
> Subject: [gem5-users] Sharing L2 cache
>
>  Hello,
>
>  How an I share two L2 caches between 4 CPU cores in GEM5.  I guess I
> have to change the code in Cacheconfig.py.
>
>  Can someone help me with this?
>
>  Thanks,
> Kumail Ahmed
>
> -- IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
>
> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
> Registered in England & Wales, Company No: 2557590
> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
> Registered in England & Wales, Company No: 2548782
>
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Re: [gem5-users] Sharing L2 cache

[Andreas Hansson via gem5-users]

Hi Kumail,

The crossbar in gem5 supports address striping, so you can create a “toL2Bus” 
that interleaves between two L2 caches. Have a look at 
config/common/MemConfig.py for how the interleaving is configured (for the 
memory channels). You should be able to do something similar.

Andreas

From: Kumail Ahmed via gem5-users 
mailto:gem5-users@gem5.org>>
Reply-To: Kumail Ahmed mailto:kumai...@gmail.com>>, gem5 
users mailing list mailto:gem5-users@gem5.org>>
Date: Tuesday, 11 November 2014 10:45
To: "gem5-users@gem5.org" 
mailto:gem5-users@gem5.org>>
Subject: [gem5-users] Sharing L2 cache

Hello,

How an I share two L2 caches between 4 CPU cores in GEM5.  I guess I have to 
change the code in Cacheconfig.py.

Can someone help me with this?

Thanks,
Kumail Ahmed

-- IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
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[gem5-users] Sharing L2 cache

[Kumail Ahmed via gem5-users]

Hello,

How an I share two L2 caches between 4 CPU cores in GEM5.  I guess I have
to change the code in Cacheconfig.py.

Can someone help me with this?

Thanks,
Kumail Ahmed
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[gem5-users] confusing cycle number

[Christian List via gem5-users]

Hello :)
Ive simulated some parsec benchmarks on an alpha architecture with gem5 on
a single core (periodically dumping stats).

For the execution I used the parameter --cpu-clock='2GHz'

In the output stat.txt I get the following parameters:

sim_seconds = 0.009517
sim_ticks = 9517306000
numCycles = 4540375

I can see here, that sim_seconds dont correlate to numCycles cause:

duration of 1 Cycle = 1 second / 2 * 10^9
number of Cycles = sim_seconds / duration of 1 cycle

When I do this by hand I get  19034000 for numCycles which is different to
the output of gem5.

I dont unterstand what I am missing :)

Best regards
Christian
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Re: [gem5-users] DRAM memory access latency

[Andreas Hansson via gem5-users]

Hi Prathap,

The crossbar has a given throughput and latency, but I think the default is 1 
Ghz, and 128-bit (16 byte) wide data patch, with a single cycle overhead (64 
bytes every 5 ns). If that is indeed a limit, then you can always increase the 
crossbar clock or width. Note that if you have very bursty reads for example 
you can easily build up a backlog.

If the crossbar is not the issue, then perhaps the master port that is the 
destination for the response is causing the problem?

Andreas

From: Prathap Kolakkampadath mailto:kvprat...@gmail.com>>
Date: Tuesday, 11 November 2014 03:41
To: Andreas Hansson mailto:andreas.hans...@arm.com>>
Cc: gem5 users mailing list mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] DRAM memory access latency

Hello Andreas,

>> waiting in the port until the crossbar can accept it

Is this because of Bus Contention? In that case, is there a way to reduce this 
latency by changing any parameters in gem5?

Thanks,
Prathap

On Thu, Nov 6, 2014 at 2:30 PM, Andreas Hansson 
mailto:andreas.hans...@arm.com>> wrote:
Hi Prathap,

I suspect the answer to the mysterious 50 ns is due to the responses being sent 
back using a so called “queued port” in gem5. Thus, from the memory 
controller’s point of view the packet is all done, but is now waiting in the 
port until the crossbar can accept it. This queue can hold a number of packets 
if there has been a burst of responses that are trickling through the crossbar 
on their way back.

You can always run with some debug flags to verify this (XBar, DRAM, 
PacketQueue etc).

Coincidentally I have been working on a patch to remove this “invisible” queue 
and should hopefully have this on the review board shortly.

Andreas

From: Prathap Kolakkampadath mailto:kvprat...@gmail.com>>
Date: Thursday, November 6, 2014 at 5:47 PM
To: Andreas Hansson mailto:andreas.hans...@arm.com>>
Cc: gem5 users mailing list mailto:gem5-users@gem5.org>>

Subject: Re: [gem5-users] DRAM memory access latency

Hello Andreas,

Thanks for your reply.


Ok. I got that the memory access latency indeed includes the queueing latency. 
And for the read/write request that miss the buffer has a static latency of  
Static frontend latency + Static backend latency.


To summarize, the test i run is a latency benchmark which is a pointer chasing 
test(only one request at a time) , generate reads to a specific DRAM bank (Bank 
partitioned).This test is running on cpu0 of 4 cpu arm_detailed running at 1GHZ 
frequency with 1MB shared L2 cache and  single channel LPDDR3 x32 DRAM. The 
bank used by cpu0 is not shared between other cpu's.

Test statistics:

system.mem_ctrls.avgQLat
   43816.35   # Average queueing delay per DRAM 
burst
system.mem_ctrls.avgBusLat5000.00   # 
Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat63816.35   # 
Average memory access latency per DRAM burst
system.mem_ctrls.avgRdQLen   2.00   # 
Average read queue length when enqueuing
system.mem_ctrls.avgGap 136814.25   # 
Average gap between requests
system.l2.ReadReq_avg_miss_latency::switch_cpus0.data 114767.654811 
  # average ReadReq miss latency

Based on above test statistics:

avgMemAccLat is 63ns, which i presume the sum of tRP(15ns)+tRCD(15ns) 
+tCL(15ns)+static latency(20ns).
Is this breakup correct?

However the l2.ReadReq_avg_miss_atency is 114ns which is ~50 ns more than the 
avgMemAccLat. I couldn't figure out the components contributing to this 50ns 
latency. Your thoughts on this is much appreciated.

Regards,
Prathap




On Thu, Nov 6, 2014 at 3:03 AM, Andreas Hansson 
mailto:andreas.hans...@arm.com>> wrote:
Hi Prathap,

The avgMemAccLat does indeed include any queueing latency. For the precise 
components included in the various latencies I would suggest checking the 
source code.

Note that the controller is not just accounting for the static (and dynamic) 
DRAM latency, but also the static controller pipeline latency (and dynamic 
queueing latency). The controller static latency is two parameters that are by 
default also adding a few 10’s of nanoseconds.

Let me know if you need more help breaking out the various components.

Andreas

From: Prathap Kolakkampadath via gem5-users 
mailto:gem5-users@gem5.org>>
Reply-To: Prathap Kolakkampadath 
mailto:kvprat...@gmail.com>>, gem5 users mailing list 
mailto:gem5-users@gem5.org>>
Date: Wednesday, 5 November 2014 05:36
To: Tao Zhang mailto:tao.zhang.0...@gmail.com>>, gem5 
users mailing list mailto:gem5-users@gem5.org>>, Amin 
Farmahini mailto:amin...@gmail.com>>
Subject: Re: [gem5-users] DRAM memory access latency

Hi Tao,Amin,

According to gem5 source, MemAccLat is the time difference between the packet 
enters in the controller and packet leaves the controller. I presume  this 
added with BusLatency and static back