Re: [gem5-users] How does scheduler work in SE mode?
There is no scheduler in SE mode. The number of hardware thread contexts (which is the same as the number of cores, unless you have SMT enabled in O3) must be = the number of software threads that get created, so each software thread gets its own dedicated hardware context and no scheduling is needed. If you need a pre-emptive thread scheduler that's a good sign you really should be running in FS mode, in my opinion. Steve On Sun, Jun 14, 2015 at 2:47 AM n26001482 n26001...@mail.ncku.edu.tw wrote: Hi, all I've run multi-thread program in ARM SE mode, and it worked well. But I'm confused how does scheduler work in SE mode? As I know there's non-OS in GEM5 SE mode and there's no scheduler in SE mode as well. So, who/what is the scheduler in charge of doing scheduling job? Thanks!! BEST M.Y. Lin ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] How does scheduler work in SE mode?
Hi, all I've run multi-thread program in ARM SE mode, and it worked well. But I'm confused how does scheduler work in SE mode? As I know there's non-OS in GEM5 SE mode and there's no scheduler in SE mode as well. So, who/what is the scheduler in charge of doing scheduling job? Thanks!! BEST M.Y. Lin ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Handle Miss cache
Hi everyone .. I'm going to disable my cpu port where the Miss occurs, in cache folder ..where is call the methods to disable ports in the base.cc in cpu folder ? thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] setting wbDepth in DerivO3CPU
Hi All, Suppose I have a CPU=DerivO3CPU(). How can I set the wbDepth parameter for this CPU. When I try CPU.wbDpeth=x, it gives an error stating AttributeError: Class DerivO3CPU has no parameter wbDepth Any help is much appreciated. Thanks Naveed Ul Mustafa ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] L2 cache partitioning
Thanks On Sat, Jun 13, 2015 at 4:38 AM, Andreas Hansson andreas.hans...@arm.com wrote: Hi Prathap, We have some patches to restrict way allocation in the cache itself (not per core though). You can probably use that as a starting point. I’m afraid beyond that you will need to add the appropriate functionality to look at e.g. masterId and decide on a way. I’ll try and get those patches posted in the next few days. Andreas From: Prathap Kolakkampadath kvprat...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.org Date: Monday, 8 June 2015 17:29 To: gem5 users mailing list gem5-users@gem5.org Subject: [gem5-users] L2 cache partitioning Dear Users, I am using ARM Full System configuration, where L2 is 8-way set associative shared Last Level Cache. I am trying to partition the L2 cache by *ways* among four cores, so that each core gets two ways. Is there a hardware support(configuration register) available to do this? If not can anyone throw some pointers to achieve way partitioning. Thanks in advance. Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] GEM_5 (Need Help in LRU implementation)
Hai , i want know the LRU Replacement algorithm how it has been using in gem5 and what are the function's, class's, they are using and my requirement is to add extra two boolean varialbles with help of them i can do my own replacement at shared last level cache, could any one help me to do these one. tanks and regards, gopi ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
