[gem5-users] Question regarding ruby network (Mesh)

[SHARJEEL KHILJI]

Hi,
I want to know that how can I get the information (that how many flits are
injected in to the network by a particular node) to the operating system. I
am running the following system,

./build/ARM/gem5.fast   configs/example/fs.py  --l1d_size=256kB
--l1i_size=256kB   --num-l2caches 16  --l2_size=128MB
--cacheline_size=64--machine-type=VExpress_GEM5_V1 --kernel
/home/khilji/gem5/m5/system/binaries/vmlinux-aarch32   --disk-image
/home/khilji/gem5/system/arm/aarch-system-20180409/disks/aarch32-ubuntu-natty-headless.img
--dtb-filename /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_16cpu.dtb
--num-cpus 16   --ruby --num-dirs=16   --network=garnet2.0--topology
Mesh_XY  --mesh-rows 4 --mem-size 1GB

I want the OS at each node to know how many flits are injected removed by
that node. Do I need to implement a particular interface which the
operating system can read?

best regards,

Muhammad
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Re: [gem5-users] Understanding how exit event is scheduled

[Utkarsh Singh]

Thank you Dr. Lowe-Power.

Sincerely,

Utkarsh Singh
Junior Undergraduate
Indian Institute of Technology - Delhi

On 14 May 2018 at 22:15, Jason Lowe-Power  wrote:

> Hi Utkarsh,
>
> I believe the exit event you are seeing is scheduled by the exit system
> call implementation. https://gem5.googlesource.com/public/gem5/+
> /master/src/sim/syscall_emul.cc#105
>
> To solve your problem, I would consider how it would be implemented in a
> "real" system. Or, if you're simply playing a trace from your new object,
> you could ignore the exit event by restarting simulation after the exit
> event from your python runscript.
>
> Hope this helps,
> Jason
>
> ---
> Jason Lowe-Power
> Assistant Professor, Computer Science Department
> University of California, Davis
> 3049 Kemper Hall
> https://faculty.engineering.ucdavis.edu/lowepower/
>
>
>
> On Mon, Apr 30, 2018 at 4:53 AM Utkarsh Singh 
> wrote:
>
>> Hi,
>>
>> As a part of my ongoing project, I am trying to understand how the exit
>> event (which is of name and description "Event Event_
>> (generic)") is being scheduled in gem5. From what I understand, at the very
>> beginning of the simulation (I am running in SE mode) an exit event is
>> scheduled at MAX_TICK = 18446744073709551615, and when the benchmark (I am
>> using a Hello World executable as a benchmark) finishes execution another
>> exit event is scheduled at curTick()+. (I observed this in
>> the eventq dump).
>>
>> Now, what my problem is that I am trying to insert a new component into
>> the architecture which reads from a text file, and is connected directly to
>> the L3 Bus (I have added an L3 layer to my architecture). However, my
>> component will be reading from the text file even after the execution of
>> the benchmark is completed. But this isn't happening because the moment the
>> benchmark finishes execution an exit event is scheduled because of which
>> the simulator stops working.
>>
>> So I was hoping whether anyone might be able to explain me the mechanism
>> of how the exit event gets scheduled, so that I may try to modify the gem5
>> code for working things out. I have tried debugging the execution using gdb
>> for the past 4 months, but I am unable to understand it due to the
>> complexity of the code. I would be really grateful if anyone is able to
>> help me out with this problem.
>>
>> Thank you.
>>
>> Sincerely,
>>
>> Utkarsh Singh
>> Junior Undergraduate
>> Indian Institute of Technology - Delhi
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[gem5-users] Response for WritebackDirty packets (learning.gem5)

[Muhammad Ali Akhtar]

Hello All,

Following jason's website, created my own cache.

On Cache miss, I send the TimingReq to memory, and get the response, which
I handle in "handleResponse".

during HandleResponse, in case the insertion causes eviction (cache was
full), the insert function generates another memPort.sendTimingReq(). This
time, the pkt is WritebackDirty. However, For this TimingReq() to memory
(WritebackDirty), we don't get any response from memory Write?

My question is:

Do we ever get a response from memory for packets of type "WritebackDirty".
When I examine the simulator output, it seems that it moves on to next
instrutions without waiting for response from memory for this particular
request.


Muhammad Ali Akhtar
Principal Design Engineer
http://www.linkedin.com/in/muhammadakhtar
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