[gem5-users] gem5 SE scheduling and virtual memory management
Dear all, I am working with gem5 SE and pthreads. I would like to verify if I have the proper understanding of the pthreads concepts in gem5. I hope you can help and discuss the points below. There is a presentation "Supporting native pthreads in syscall emulation mode" on gem5 website, but I cannot find the paper anywhere. Here are my questions/constatations: 1. pthread support is fully emulated inside of the gem5 SE, meaning there is no forwarding of the pthread calls to the host operating system? 2. I understand that the gem5 uses two dimensional time, where for one tick several events are created, to simulate concurrent execution of threads. However, I do not understand the scheduling management of threads. Who is creating the events? Is there a pre-emption of threads allocated at the same hardware unit, and if yes, who is doing the scheduling management? 3. Is there any virtual memory isolation between threads, or because we have only one process running several threads, the memory is directly mapped to the physical (simulated) memory of gem5? Best regards, Jasmin JAHIC ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Regression Test Always Fails, Cannot Find Path
Thanks a lot. By the way, I want to know how to run regression tests. It seems the regression test depends on SPEC CPU2000 heavily. I have the SPEC CPU2000 & 2006 suite. But I still don't understand how to make it work... The document site http://gem5.org/SPEC_benchmarks provides such information: Workloads created from this package expect to find their binaries and input files in the following two directories, respectively. cpu2000/binaries/// cpu2000/data// But there isn't an example. To my understanding, an example of the mcf benchmark should be : cpu2000/binaries/x86/linux/mcf cpu2000/binaries/mcf/ref cpu2000/binaries/mcf/ test cpu2000/binaries/mcf/train These are so-called directories. And there should be files in these directories. For instance, cpu2000/binaries/x86/linux/mcf/mcf, the latter mcf is a file. Or maybe I should use cpu2000/binaries/x86/linux/mcf, just the mcf program, no additional path. I have tried both methods but failed. The regress.py just throws: AttributeError: /home/zheng/SPEC2000_v13/binaries/x86/linux/mcf not found. But the file is just there. I don't know what happened. BTW, I have a question about the naming methods of gem5: when to use UPPERCASE in paths and file names? Sometimes, I need to use "X86", "ALPHA". While other times I need to use "x86", "alpha". Frankly speaking, it is terrible! Best Regards Zheng Liang EECS, Peking University -Original Messages- From:"Daniel Carvalho" Sent Time:2018-11-10 22:51:56 (Saturday) To: gem5-users@gem5.org, "梁政" Cc: Subject: Re: How to modify the Cache Timing Model ? Hello Liang, The cache timing model is something that me, Jason and Nikos have been recently discussing. You can follow part of the discussion on the following links: https://gem5-review.googlesource.com/c/public/gem5/+/13697 and https://gem5-review.googlesource.com/c/public/gem5/+/13835. Reworking the timing model to be more accurate and flexible is a hard task, and you will likely just want to modify code related to timing, as the latency in atomic mode is not well defined (in the sense of how correct it should be; There is no clear answer). I'd suggest you to look at these patches and their evolution to have and idea of the decisions that you may or may not want to take (I am not saying they are the right way to do it, though). Regarding the Tags, we currently have 3 sub-classes: BaseSetAssoc, FALRU and SectorTags. Although we can think of FALRU as a subset of BaseSetAssoc (and you can definitely create a full associative tag using BaseSetAssoc), FALRU has its own implementation, which leverages from hashes and the awareness of a single replacement policy (LRU), because otherwise the cost of checking every block would be too high for greater cache sizes. Regards, Daniel Em sexta-feira, 9 de novembro de 2018 22:00:59 GMT+1, 梁政 escreveu: Hi I am reading the latest code of gem5 and try to make the cache model more flexible (e.g., allowing non-constant access latency). So I will change the timing behavior of the Cache class. Currently, I am reading the code in /mem/cache. I found that two major classes have their timing model: the Cache/NoncoherentCache/BaseCache family and the Tag family. So what I need to do is to change related codes with a device timing model, right? Or there may be other points I missed? Thanks for your advice. BTW, what are the FALRU tags for? It seems all configurations use SetAssoc Tags. I found a paper from UC.Berkeley. It is related to Sector Cache. Maybe someone will use that model in the future. But why should Fully-associative LRU cache be considered separately? Regards Zheng Liang EECS, Peking University___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] How to modify the Cache Timing Model ?
Hello Liang, The cache timing model is something that me, Jason and Nikos have been recently discussing. You can follow part of the discussion on the following links: https://gem5-review.googlesource.com/c/public/gem5/+/13697 and https://gem5-review.googlesource.com/c/public/gem5/+/13835. Reworking the timing model to be more accurate and flexible is a hard task, and you will likely just want to modify code related to timing, as the latency in atomic mode is not well defined (in the sense of how correct it should be; There is no clear answer). I'd suggest you to look at these patches and their evolution to have and idea of the decisions that you may or may not want to take (I am not saying they are the right way to do it, though). Regarding the Tags, we currently have 3 sub-classes: BaseSetAssoc, FALRU and SectorTags. Although we can think of FALRU as a subset of BaseSetAssoc (and you can definitely create a full associative tag using BaseSetAssoc), FALRU has its own implementation, which leverages from hashes and the awareness of a single replacement policy (LRU), because otherwise the cost of checking every block would be too high for greater cache sizes. Regards,Daniel Em sexta-feira, 9 de novembro de 2018 22:00:59 GMT+1, 梁政 escreveu: Hi I am reading the latest code of gem5 and try to make the cache model more flexible (e.g., allowing non-constant access latency). So I will change the timing behavior of the Cache class. Currently, I am reading the code in /mem/cache. I found that two major classes have their timing model: the Cache/NoncoherentCache/BaseCache family and the Tag family. So what I need to do is to change related codes with a device timing model, right? Or there may be other points I missed? Thanks for your advice. BTW, what are the FALRU tags for? It seems all configurations use SetAssoc Tags. I found a paper from UC.Berkeley. It is related to Sector Cache. Maybe someone will use that model in the future. But why should Fully-associative LRU cache be considered separately? Regards Zheng Liang EECS, Peking University ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Doubts in packet and request
On Sat, Nov 10, 2018, 12:05 Riddhi Thakker wrote: > Hello all, > > I have observed that when I run benchmarks, the size of the packet is > always 64 bytes. Where as if I run small SE programs the sizes turns out to > be different. If I call an instruction of 'int' size, it will not call the > packet of size 64 bytes, it should be lesser. > Following are my questions: > 1) Why every time the packet size is 64 when I run a benchmark ? > In gem5, every memory access is modelled in terms of packets. And the processor accesses memory at the granularity of cache line size, which is 64bytes. Hence, you will see 64bytes of data in each packet. > 2) The packet which is created refer to only one instruction (i.e. one > request) or multiple ? > An instruction can require any amount of data, and hence would need multiple packets to serve it, since a single packet gives just 64bytes. > 3) If packet refers to only one instruction or request then how come for > all the kind of instructions is the packet size same ? > As explained earlier, a packet can be mapped to a single instruction only. And the packet size is the cache line size. > 4) If a packet refers to different instructions or requests then how do I > infer how much data bytes do each instruction wants? > To quantify the amount of data accessed by an instruction, get the total number of packets mapped to that instruction. Amount of data = (number of packets * 64) in bytes. > 5) When I am trying to explicitly use the getReqInstSeqNum() function, > then why it gives me assertion failed error for VALID_INST_SEQ_NUM ? > Is this function trying to fetch the instruction sequence in the instruction queue? > > I really want to get answers for these questions. It will be a great help > to me if anyone can get through this. > > Thanks in advance. > > Regards, > Riddhi Thakker > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Best Regards, Sarabjeet Singh ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
