Re: [gem5-users] (no subject)
What you do, is create flags in src/mem/packet.hh for various cache levels. Whenever you hit in L2, you can set the L2flag in response pkt. And if it is misses in L2, set main memory flag in response pkt, as you are sure you will get data from main memory. Here we are assuming it’s a single core simulation. On Fri, May 10, 2019 at 5:42 AM Muhammad Avais wrote: > Dear All, > > 1- For blocks loaded in the L1 cache, how can I distinguish that it was > loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1 > cache)? > > Many thanks, > Best Regards, > Avais > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Bypassing blocks to LLC
Hi Richard, What you can do is, wherever your desired block reaches at L3 level in the form of a packet that is in “recvTimingReq” function, instead of writing in L3. Create a write-back queue entry at L3 for that pkt and then it should automatically go to Main memory. On Thu, May 2, 2019 at 7:08 PM Richard Brown wrote: > Hello everyone, > > I am PhD student and new with gem5, I have a multicore system with 2 > private cache levels (DL1, IL1 and L2) and 1 shared L3/LLC. I am using > classic memory system, I know this model is non-inclusive, non-exclusive. > > For my research I need to bypass some blocks from L3, I mean when some > blocks are read I want to write them to L1 and L2 and not write them in L3, > and when some blocks are evicted from L2, if they are dirty, I want to > write them to Main Memory and not to L3. > > Is it possible to bypass some blocks from L3 reading the accesses > messages? I think I just need to change cache.cc, is it right? > > I really apreciate your help, thanks in advance. > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] (no subject)
Hi Muhammad,
One way is to use the function "name()" in src/mem/cache/base.cc and
src/mem/cache/cache.cc file to implement cache specific function.
For e.g.,
for implementing things specifically for dcache u can just write if
(name() == "system.cpu.dcache"){ }
Best regards,
Abhishek
On Fri, May 10, 2019 at 5:23 AM Muhammad Avais
wrote:
>Dear All,
>
> I have one question. For blocks loaded in the L1 cache, how can I
> distinguish that it was loaded into the L1 cache from L2 cache or main
> memory?
>
> Many thanks,
> Best regards,
> Avais
>
>
> On Wed, May 8, 2019 at 5:21 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi Muhammad,
>>
>>
>> If you want on L2 hit, the block is invalidated from L2 cache and filled
>> in Dcache and the rest behavior same as you explained in the diagram, you
>> can use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file.
>> You may need to take care of "clean victim" from dcache which is not a
>> difficult modification.
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Tue, May 7, 2019 at 1:48 AM Muhammad Avais
>> wrote:
>>
>>> Dear All,
>>> Is 'mostly exclusive cache' supported in GEM5 classic model
>>> strictly non-exclusive cache? If it is not non-exclusive cache, how can I
>>> make it non-exclusive cache?
>>>
>>> The non-exclusive cache is shown in Fig. below.
>>> [image: image.png]
>>> Can anyone guide me?
>>>
>>> Many thanks,
>>> best regards,
>>> Avais
>>>
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
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[gem5-users] (no subject)
Dear All, 1- For blocks loaded in the L1 cache, how can I distinguish that it was loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1 cache)? Many thanks, Best Regards, Avais ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] (no subject)
Dear All, I have one question. For blocks loaded in the L1 cache, how can I distinguish that it was loaded into the L1 cache from L2 cache or main memory? Many thanks, Best regards, Avais On Wed, May 8, 2019 at 5:21 AM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hi Muhammad, > > > If you want on L2 hit, the block is invalidated from L2 cache and filled > in Dcache and the rest behavior same as you explained in the diagram, you > can use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file. > You may need to take care of "clean victim" from dcache which is not a > difficult modification. > > Best regards, > > Abhishek > > > On Tue, May 7, 2019 at 1:48 AM Muhammad Avais > wrote: > >> Dear All, >> Is 'mostly exclusive cache' supported in GEM5 classic model >> strictly non-exclusive cache? If it is not non-exclusive cache, how can I >> make it non-exclusive cache? >> >> The non-exclusive cache is shown in Fig. below. >> [image: image.png] >> Can anyone guide me? >> >> Many thanks, >> best regards, >> Avais >> >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
