[gem5-users] simulate() limit problem when I'm running openmp benchmarks on gem5

[汪翔]

Hi all,

I have compiled openmp benchmarks using m5threads. command lines are as follow:

"./build/X86/gem5.opt configs/example/se.py -n 4 -c ../m5threads/tests/test_omp 
-o '2 2' --caches --l2cache --l1d_size=128kB --l1i_size=128kB --l2_size=1MB 
--l1d_assoc=2 --l1i_assoc=2 --l2_assoc=1 --cacheline_size=64"

I got this message on the terminal:

info: Entering event queue @ 0.  Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in 
various settings.
  Returning '/home/wangxiang/gem5_my/m5threads/tests/omp_true'
info: Increasing stack size by one page.
warn: ignoring syscall access(...)
Setting OMP threads to 2
Starting with row/col size=2
A initialized
B initialized
Computing A*B with 2 threads
warn: ClockedObject: Already in the requested power state, request ignored
Done
Exiting @ tick 18446744073709551615 because simulate() limit reached 

stats.txt are as follow:

sim_seconds  18446744.073710   
# Number of seconds simulated
sim_ticks18446744073709551616   
# Number of ticks simulated
final_tick   18446744073709551616   
# Number of ticks from beginning of simulation (restored from checkpoints 
and never reset

The problem is that I want to get correct sim_seconds of test_omp, but 
"sim_seconds 18446744.073710" is impossible. It seems like openmp program has 
stalled somewhere. But when I test it on my own computer, it works well and 
exits correctly. What should I do to get the true stats of my bench?

Any help will be appreciated!
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[gem5-users] Full-system experiments with MOESI AMD Base Protocol

[Pouya Fotouhi]

Hi Everyone,

I'm wondering if anyone has used the MOESI AMD Base protocol to run
full-system experiments?

For the DMA controller, I used the implementation from GCN3 staging branch
 but
my experiments encounter live-locks during the bootup.

Best,
-- 
Pouya Fotouhi
PhD Candidate
Department of Electrical and Computer Engineering
University of California, Davis
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Re: [gem5-users] Compressor

[Daniel Carvalho]

Hello Pooneh,

There is currently no support for compressed L1 caches (and there is no plan to 
add, since it would require great modifications to the caches), therefore if 
you setup the configuration in src/mem/cache/Cache.py it is going to break it 
(it sets for all caches, including L1).

What you want is to create your own config file (Jason's website can help you 
with that) that sets the L2 (L3,L4...; as many as you want) as compressed. A 
quick and VERY dirty fix just to check if it works would be to add the 
compression parameters (tags = CompressedTags() \n compressor = BDI()) to 
L2Cache in configs/common/Caches.py (Again, you'd better create your own config 
file; it takes a bit of time, but it is worth it).


By the way, you might want to check out the other existing debug flags for 
caches too (src/mem/cache/SConscript).


Regards,
Daniel
   Em quinta-feira, 16 de maio de 2019 21:11:03 GMT+2, Pooneh Safayenikoo 
 escreveu:  
 
 Hi,
I installed a new version of Gem5 that has compression patches. So, I changed 
Null to BDI() for compressor in src/mem/cache/Cache.p. but I have a 
segmentation fault when I write a --caches or --l2cache in the command line. I 
wrote dprintf to print data in l2 by adding cache for debug-flage but there is 
nothing in trace file. Could you please tell me how I can fix it?  

Many Thanks!
Best,Pooneh    ___
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Re: [gem5-users] Update an architectural register on eviction from dCache

[Abhishek Singh]

Has anyone used Model Specific register in caches?
That is, to set single bit value in any of the MSR from caches?

Best regards,

Abhishek


On Wed, May 15, 2019 at 2:54 PM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hello Everyone and Gabe,
>
> I am having difficulty in finding a way to implment a new register in X86
> ISA which is set one when an eviction occurs in dCache.
>
> Does anyone know which files, I should look into or any suggestions on how
> to achieve this implementation?
>
>
> Best regards,
>
> Abhishek
>
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