Re: [gem5-users] Victim Cache in Ruby
MOESI protocol (MOESI_AMD_Base) models L3 caches as victim caches. Depending on the configuration you want to use, you may be able to use it. Best, On Fri, May 17, 2019 at 11:18 AM S M Farabi Mahmud wrote: > I was planning to make a Victim Cache using the ruby memory system. How to > proceed with that? > > I have seen emails where regular victim cache is mentioned. I need Victim > Cache which also supports ruby. > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Pouya Fotouhi PhD Candidate Department of Electrical and Computer Engineering University of California, Davis ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Victim Cache in Ruby
I was planning to make a Victim Cache using the ruby memory system. How to proceed with that? I have seen emails where regular victim cache is mentioned. I need Victim Cache which also supports ruby. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Update an architectural register on eviction from dCache
Thank you! This information helps a lot ! On Fri, May 17, 2019 at 2:13 PM Gabe Black wrote: > Hi Abhishek. You would probably want accesses to the MISCREG_* to go find > the cache and ask it what value to reply with instead of the other way > around. The system doesn't necessarily have caches or a particular number > or topology of caches, so you'll likely need to set up some custom plumbing > so the register code and the cache code can find each other in your setup. > > Gabe > > On Thu, May 16, 2019, 10:47 AM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >> Has anyone used Model Specific register in caches? >> That is, to set single bit value in any of the MSR from caches? >> >> Best regards, >> >> Abhishek >> >> >> On Wed, May 15, 2019 at 2:54 PM Abhishek Singh < >> abhishek.singh199...@gmail.com> wrote: >> >>> Hello Everyone and Gabe, >>> >>> I am having difficulty in finding a way to implment a new register in >>> X86 ISA which is set one when an eviction occurs in dCache. >>> >>> Does anyone know which files, I should look into or any suggestions on >>> how to achieve this implementation? >>> >>> >>> Best regards, >>> >>> Abhishek >>> >> ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] ARM 32/64 Core FS Simulation - No BOOTUP
Hi Ciro, I still not able to boot (32 cores) with the version you recommended. I also tried to use the auto generated dtb, but that didn't help either. Regards Yasir -Original Message- From: Ciro Santilli [mailto:ciro.santi...@arm.com] Sent: 15 May 2019 17:51 To: Qureshi Yasir Mahmood ; gem5 users mailing list Subject: Re: [gem5-users] ARM 32/64 Core FS Simulation - No BOOTUP On 5/14/19 3:06 PM, Qureshi Yasir Mahmood wrote: > Hi All, > > I am trying to do a 32/64 core ARMv8 FS simulation. I have followed > the steps in > https://www.mail-archive.com/gem5-users@gem5.org/msg15475.html > and also enabled the GICv2 extensions fs.py file. The simulation does > not boot-up, and is stalled/hanged-up in the boot process. I am using > kernel 4.15. The command line is as follows > > ./build/ARM/gem5.fast --remote-gdb-port=0 -d test_32_cores > configs/example/fs.py --cpu-clock=1GHz --kernel=vmlinux4_15 > --machine-type=VExpress_GEM5_V1 > --dtb-file=/home/yqureshi/gem5/system/arm/dt/armv8_gem5_v1_32cpu.dtb > -n > 32 --disk-image=test_32.img --caches --l2cache --l1i_size=32kB > --l1d_size=32kB --l2_size=1MB --l2_assoc=2 --mem-type=DDR4_2400_4x16 > --mem-ranks=4 --mem-size=4GB --sys-clock=1600MHz > > Has anyone encountered a similar issue and resolved it? Just to > mention, the simulation works well for up to 16 cores. > Hi Qureshi, I have just successfully booted the gem5 4.15 kernel with gem5 9048ef0ffbf21bedb803b785fb68f83e95c04db8 and command line: build/ARM/gem5.opt \ --debug-file trace.txt \ --listener-mode on \ --outdir out/run/gem5/aarch64/0/m5out \ submodules/gem5/configs/example/fs.py \ --disk-image rootfs.ext2 \ --kernel gem5-v4.15/aarch64/vmlinux \ --mem-size 256MB \ --num-cpus 32 \ --script readfile \ --command-line 'earlyprintk=pl011,0x1c09 lpj=19988480 rw loglevel=8 mem=256MB root=/dev/sda console_msg_format=syslog nokaslr norandmaps panic=-1 printk.devkmsg=on printk.time=y rw console=ttyAMA0 - lkmc_home=/lkmc' \ --machine-type VExpress_GEM5_V1 \ --param 'system.panic_on_panic = True' \ --param 'system.realview.gic.gem5_extensions = True' \ ; Can you try to diff out the command lines? The most important difference I see is that I'm not passing a DTB, which enables automatic DTB generation, which is more likely to be correct than the manually created one. This had also been recommended at: https://stackoverflow.com/a/50248068/9160762 > Best Regards > > Yasir > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
