[gem5-users] Remote gdb debug interface for RISCV/gem5.debug
Hi, colleges,
I'm trying to use remote gdb debug for RISCV/gem5.debug in FS mode. The
binaries file I used to try this interface is the Berkely boot loader and
it has been able to boot in FS mode.
* I enabled the "wait_for_remote_gdb" Params in BaseCPU.py and this Params
worked.
But GDB part (riscv64-unknown-elf-gdb) returned glitch.
* I tried the "hello world" binary with riscv64-unknown-elf-gdb in SE mode.
The similar glitch happened.
* I also tried the remote debug the Berkeley boot loader in Qemu with the
same gdb tool. It works.
Did I pick the wrong Riscv GDB tool for gem5? Did I miss anything?
Any opinion will be helpful. I appreciate your time and help!
Attached are the commands I used and the message I got:
** Commands
*** The command I used for FS mode is :
build/RISCV/gem5.debug configs/example/riscv_fs.py
*** The command I used for remote gdb is:
riscv64-unknown-elf-gdb -f bbl3
(gdb) target remote : 7000
** Messages
*** The message I got from Gem5:
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 17 2019 11:55:28
gem5 started Jul 17 2019 11:59:25
gem5 executing on riscv_fs, pid 14710
command line: build/RISCV/gem5.debug configs/example/riscv_fs.py
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (32768 Mbytes)
info: kernel located at: /home/ riscv_fs/gem5/gem5_ad2039/bbl3
0: system.remote_gdb: listening for remote gdb on port 7000
info: system.cpu: Waiting for a remote GDB connection on port 7000.
0: system.remote_gdb: remote gdb attached
start load DTB file/home/riscv_fs/gem5/gem5_ad2039/cpu.dtb
Beginning simulation!
info: Entering event queue @ 0. Starting simulation...
warn: Couldn't read data from debugger.
0: system.remote_gdb: remote gdb detached
This is bbl's dummy_payload. To boot a real kernel, reconfigure bbl
with the flag --with-payload=PATH, then rebuild bbl. Alternatively,
bbl can be used in firmware-only mode by adding device-tree nodes
for an external payload and use QEMU's -bios and -kernel options.
chosen {
riscv,kernel-start = ;
riscv,kernel-end = ;
};
*** message I got from gdb is:
Remote debugging using : 7000
Remote 'g' packet reply is too long (expected 532 bytes, got 1468 bytes):
2010008003002d1114200a003f702f5d070
Re: [gem5-users] questions about template policies in O3CPU
Hello, the lsq_unit, as long as other basic parts in the pipeline (i.e., fetch, decode etc) are generally defined as template classes as you said. The equivalent *.c files instantiate the object by calling with a specific argument, in this case with the "O3CPUImpl" argument. These .c files are the ones that include the necessary header files and are given as source for compilation in the SConscript file, for instance in the one in the o3 folder, when it comes to the o3 model. Hope it helps. Regards, -- Kleovoulos Kalaitzidis Doctorant - Équipe PACAP Centre de recherche INRIA Rennes - Bretagne Atlantique Bâtiment 12E, Bureau E321, Campus de Beaulieu, 35042 Rennes Cedex, France > From: "yuan" > To: "gem5 users mailing list" > Sent: Tuesday, July 16, 2019 10:59:46 PM > Subject: [gem5-users] questions about template policies in O3CPU > Hi, all, > I am trying to understand the O3CPU code. But I find that the template policy > is > heavily used in O3CPU and I am quiet confused about this part. Like the load > store queue, the lsq_unit.hh file has all the class declaration of lsq_unit, > but in the lsq_unit.cc file, there is only one statement “template class > LSQUnit;”. My understanding is that all the functions in > lsq_unint.hh are actually defined/implemented in lsq_unit_impl.hh files. The > O3CPUImpl is actually defined in impl.hh file. But what the lsq_unit.cc file > is > actually doing? And what is the design model behind this template usage? Does > anyone know about this part. Thanks so much. > Best regards. > Yuan > Sent from [ https://go.microsoft.com/fwlink/?LinkId=550986 | Mail ] for > Windows > 10 > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] problem about system membus
Hi all, I have some questions about membus of the system 1.where is definition of system.membus?I have found System.py in gem5/src/system.py.But I haven't found definition of membus there.Besides,what file contains information about how to use membus? 2.For SystemXBar() which instantiates system.membus,Is the value of frontend_latency（3），forward_latency（4），response_latency（2），snoop_response_latency（4）close to real delay of membus?I heard that delay of membus may be about 100 cycles. Any help will be appreciated! ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] ARMv8 64 FS Linux Boot issue with 2 or more cores in HPI Model
I reproduced the problem, and for my own sanity will keep track of it unofficially at: https://github.com/cirosantilli/linux-kernel-module-cheat/issues/77 However, the bisection led to a seemingly benign commit, and when I tried on a different host machine I was not able to reproduce anymore, which suggests that it is an undefined behavior issue on our C++ code, so it might be hard to solve. Alternatively, could you instead boot with the Atomic CPU, checkpoint, and then restore HPI? On Fri, Jul 12, 2019 at 6:28 PM Chakraborty, Prasen wrote: > > Hi, > > I am trying to get Linux boot up in gem5 ARMv8 64 > configuration with the “HPI” CPU model. Though I am able to successfully boot > with num_cores=1 or AtomicSimpleCPU model and num_cores=8. The problem seems > to be the combination of HPI/Minor etc with num_cores=2 or more. The kernel > is hanging during various stages of the booting for each run. > > > > I am using the Kernel and Disk Image located at : > http://www.gem5.org/dist/current/arm/ aarch-system-20180409.tar.xz (as well > aarch-system-20170616.tar.xz) > > > > To solve the issue I have tried building my own kernel and boot loader image > and the DTB file as mentioned in http://gem5.org/ARM_Kernel. However the same > problem persists. I have tried various solutions mentioned in other thread > chains and basically tried the following commands : > > > > ./build/ARM/gem5.opt configs/example/arm/starter_fs.py --cpu="hpi" > --num-cores=2 --kernel=vmlinux.vexpress_gem5_v1_64 > --disk-image=/home/pchakra1/Workspace/Benchmarks/LinuxKernels/20180409/disks/linaro-minimal-aarch64.img > > --dtb=/home/pchakra1/Workspace/PublicRepo/gem5/system/arm/dt/armv8_gem5_v1_2cpu.dtb > > > > > > ./build/ARM/gem5.opt configs/example/fs.py > --kernel=vmlinux.vexpress_gem5_v1_64 --cpu-type="HPI" -n 2 --caches --l2cache > --machine-type=VExpress_GEM5_V1 --param 'system.realview.gic.gem5_extensions > = True' > --dtb-file=/home/pchakra1/Workspace/Benchmarks/LinuxKernels/20180409/binaries/armv8_gem5_v1_8cpu.dtb > > --disk-image=/home/pchakra1/Workspace/Benchmarks/LinuxKernels/20180409/disks/linaro-minimal-aarch64.img > > > > > > Any pointers how to get around this will be highly appreciated. I do need the > Performance CPU model for my studies. > > > > Regards, > > Prasenjit > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
