[gem5-users] Questions about simulation configure!
Hi, all, I have one question about simulation configurations. We know that all simulation parameters are setting through python files. But eventually these parameters must be sent to somewhere to generate objects using the c++ files. I tried to find these code in src/sim directory but find nothing there? Does anyone knows about this? Thank you so much. Best regards. Yuan Sent from Mail for Windows 10 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Full system simulation freeze
Hmm... that's strange. I would expect that command line to be completely deterministic. However, Brandon just submitted a patch that fixes an undefined behavior error for x86. It should be merged soon, but if you'd like to try it now see https://gem5-review.googlesource.com/c/public/gem5/+/19568 Cheers, Jason On Thu, Jul 18, 2019 at 11:55 AM Armel Jeatsa wrote: > Hello, > I use the command : *build/X86/gem5.opt configs/example/fs.py > --disk-image=$(pwd)/full-system-images/disks/linux-x86.img > --kernel=$(pwd)/full-system-images/binaries/x86_64-vmlinux-2.6.22.9.smp > --cpu-type=TimingSimpleCPU -n 4 --caches --l1i_size=8kB --l1d_size=8kB > --l2cache --l2_size=256kB* > and it seems to freeze at line : *"Brought up 4 CPUs"* > > kind regards, > Armel > -- > *JEATSA TOULEPI Armel* > Étudiant En Génie Informatique > Tel: +237 650771894 / 655296800 > > > Le lun. 15 juil. 2019 à 17:22, Jason Lowe-Power a > écrit : > >> Hi Armel, >> >> It's unlikely the performance of the host machine. gem5 should be >> deterministic, and the underlying host machine shouldn't make a difference. >> >> Since you're seeing non-deterministic behavior, you should ask "what >> about the simulation is changing?". Is it some configuration options (e.g., >> size of caches)? Is it the CPU pipeline design (e.g., size of ROB)? This >> might give a hint as to the problem. >> >> If you could give us details about your configuration (e.g., Ruby vs >> classic caches, what CPU model, etc.) we may be able to help more. >> >> Cheers, >> Jason >> >> On Mon, Jul 15, 2019 at 1:39 AM Armel Jeatsa >> wrote: >> >>> Hello everyone, >>> >>> Sometimes when i launch full system simulation, the process seems to be >>> freezing at line "*Brought up 2 CPUs*" or at line "*Freeing unused >>> kernel memory: 248k freed*", and other times it launches well and show >>> the m5 terminal. What can be the cause of the problem?? could it be >>> related to the performance of my machine? >>> >>> Kind regards, >>> Armel. >>> -- >>> *JEATSA TOULEPI Armel* >>> Étudiant En Génie Informatique >>> Tel: +237 650771894 / 655296800 >>> ___ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Full system simulation freeze
Hello, I use the command : *build/X86/gem5.opt configs/example/fs.py --disk-image=$(pwd)/full-system-images/disks/linux-x86.img --kernel=$(pwd)/full-system-images/binaries/x86_64-vmlinux-2.6.22.9.smp --cpu-type=TimingSimpleCPU -n 4 --caches --l1i_size=8kB --l1d_size=8kB --l2cache --l2_size=256kB* and it seems to freeze at line : *"Brought up 4 CPUs"* kind regards, Armel -- *JEATSA TOULEPI Armel* Étudiant En Génie Informatique Tel: +237 650771894 / 655296800 Le lun. 15 juil. 2019 à 17:22, Jason Lowe-Power a écrit : > Hi Armel, > > It's unlikely the performance of the host machine. gem5 should be > deterministic, and the underlying host machine shouldn't make a difference. > > Since you're seeing non-deterministic behavior, you should ask "what about > the simulation is changing?". Is it some configuration options (e.g., size > of caches)? Is it the CPU pipeline design (e.g., size of ROB)? This might > give a hint as to the problem. > > If you could give us details about your configuration (e.g., Ruby vs > classic caches, what CPU model, etc.) we may be able to help more. > > Cheers, > Jason > > On Mon, Jul 15, 2019 at 1:39 AM Armel Jeatsa > wrote: > >> Hello everyone, >> >> Sometimes when i launch full system simulation, the process seems to be >> freezing at line "*Brought up 2 CPUs*" or at line "*Freeing unused >> kernel memory: 248k freed*", and other times it launches well and show >> the m5 terminal. What can be the cause of the problem?? could it be >> related to the performance of my machine? >> >> Kind regards, >> Armel. >> -- >> *JEATSA TOULEPI Armel* >> Étudiant En Génie Informatique >> Tel: +237 650771894 / 655296800 >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Issue with O3PipeView in latest gem5
Hi, Can anyone please confirm whether the O3PipeView is working properly in the least gem5 repo or its something wrong with me. It used to work earlier. Currently while trying to generate the Pipeline trace for ARM detailed CPU model, I am getting an empty trace.out file. ./build/ARM/gem5.opt --debug-flags=O3PipeView --debug-start=50 --debug-file=trace.out configs/example/se.py -cpu-type=detailed --caches -c nop.out -m 100 REAL SIMULATION info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Exiting @ tick 100 because simulate() limit reached ls -l m5out drwxrwxr-x 3 pchakra1 pchakra1 4096 Jul 18 10:21 ./ drwxrwxr-x 15 pchakra1 pchakra1 4096 Jul 18 10:21 ../ -rw-rw-r-- 1 pchakra1 pchakra1 11242 Jul 18 10:21 config.ini -rw-rw-r-- 1 pchakra1 pchakra1 30245 Jul 18 10:21 config.json drwxrwxr-x 5 pchakra1 pchakra1 4096 Jul 18 10:21 fs/ -rw-rw-r-- 1 pchakra1 pchakra1 71553 Jul 18 10:21 stats.txt -rw-rw-r-- 1 pchakra1 pchakra1 0 Jul 18 10:21 trace.out The executable runs much beyond 100 ticks, so the start and end ticks looks correct to me. I've tried various start/end but nothing works! Has the usage changed lately? What needs to be changed if I want to use the minorview with the Minor model instead of O3? I don't see corresponding debug-flags except "MinorCPU". Regards, Prasenjit ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] RISC-V DerivO3CPU: Assertion `atomicOpFunctor != NULL' failed
Forwarding a possible solution:
-- Forwarded message -
Hi Hossein,
I don't know if there is an update to this on you end, but here is how I
got around this issue when I tried running some SPEC benchmarks compiled
for RISC-V on DerivO3CPU.
I guess the problem is related to how Packet objects are created and sent
to the cache from the LSQ. I've debugged a bit and found that the
problematic AtomicOpFunctor pointer is valid up to the point where the LSQ
calls "req->buildPackets();" (@lsq_unit_impl.hh:771). Packets built by this
call won't have the AtomicOpFunctor in their Request objects and this is
the cause of the problem. I couldn't find an elegant way to handle this but
basically what I did was to modify Request class so that I was able to set
the AtomicOpFunctor in LSQ before the packet is sent to the cache. Here are
the modifications I've made.
+++ b/src/cpu/o3/lsq_unit_impl.hh
> @@ -771,10 +771,14 @@ LSQUnit::writebackStores()
> req->buildPackets();
>
> DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
> -"to Addr:%#x, data:%#x [sn:%lli]\n",
> +"to Addr:%#x, data:%#x [sn:%lli] amoOp:%d\n",
> storeWBIt.idx(), inst->pcState(),
> req->request()->getPaddr(), (int)*(inst->memData),
> -inst->seqNum);
> +inst->seqNum, req->_amo_op != NULL);
> +
> +
> +if(req->_amo_op != NULL)
> +req->request()->setAtomicOpFunctor(req->_amo_op);
>
> // @todo: Remove this SC hack once the memory system handles it.
> if (inst->isStoreConditional()) {
>
> +++ b/src/mem/request.hh
> @@ -679,6 +679,12 @@ class Request
> return atomicOpFunctor;
> }
>
> +void
> +setAtomicOpFunctor(AtomicOpFunctor* atm)
> +{
> +atomicOpFunctor = atm;
> +}
> +
> /** Accessor for flags. */
> Flags
> getFlags()
>
Ideally I'd like to respond to the thread you've posted on the mailing list
but I don't know if I am able to do it.
Thanks,
Ataberk
On Thu, Jun 13, 2019 at 12:28 PM Hossein Golestani
wrote:
> Hi,
>
> I'm using gem5 for simulation of cross-compiled RISC-V programs.
>
> I receive the following error when using the DerivO3CPU model:
> gem5.opt: build/RISCV/mem/request.hh:678: AtomicOpFunctor*
> Request::getAtomicOpFunctor(): Assertion `atomicOpFunctor != NULL' failed.
>
> I have used this command:
> $GEM5/build/RISCV/gem5.opt --outdir=$OUTDIR \
> $GEM5/configs/example/se.py \
> --cpu-type=DerivO3CPU \
> --l1d_size=64kB \
> --l1i_size=16kB \
> --l2_size=1MB \
> --caches \
> --l2cache \
> --cmd=$BINARY --options="$OPTIONS"
>
> If I fast-forward the beginning instructions of the program, I will
> receive the exact same error at some point later.
>
> Note that I have no issues with simulating this program with the
> TimingSimpleCPU model.
>
> I found this email (link
> ) in the
> gem5 user emails archive, which says the O3 CPU model may have not been
> tested with RISC-V. However I'd really appreciate any help to get around
> this issue. I have started to work with gem5 for a few weeks, but I'm
> willing to modify its code if necessary.
>
> Thanks,
> Hossein
>
>
>
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