Re: [gem5-users] ARM DerivO3CPU assertion failed

[Carlos Escuin]

I've been trying to dig in more in the code... I think there is a bug 
when the ArmTLB is trying to switch to the Ruby memory subsystem.


Is anyone having any trouble with this aswell?


Carlos

On 21/2/20 15:59, Ciro Santilli wrote:

I observe the following behavior on se.py ARM and X86, which depends on
--restore-with-cpu. I have used a minimal userland executable that only
does two things in assembly: m5 checkpoint and m5 exit (total of only 5
instructions in aarch64)

@Jason: can you confirm the difference between se.py --restore-with-cpu
and --cpu-type during a checkpoint restore (and if any of the outcome
below are buggy or not)? At
https://stackoverflow.com/questions/49011096/how-to-switch-cpu-models-in-gem5-after-restoring-a-checkpoint-and-then-observe-t 


it was mentioned that --restore-with-cpu
should be the old CPU (defaults to AtomicSimpleCPU), and --cpu-type the
new CPU, is that correct? Asking because I have observed less failures
if I set --restore-with-cpu to equal --cpu-type.

I'll open/update clear bugs with the test binaries for any behavior
which is not correct.

== Default Build

Restore with: --cpu-type DerivO3CPU
Outcome: gem5 crashes: panic: Attempted to execute unknown instruction
(inst 0x)

Restore with: --cpu-type DerivO3CPU --restore-with-cpu DerivO3CPU
Outcome: works

== MESI_Three_Level build

Checkpoint run with: --ruby
Outcome: hangs forever when taking the checkpoint.

Checkpoint run at the commit before
bb94296373dde1d0ce971ee58ad111f4225c425e (which
https://gem5.atlassian.net/projects/GEM5/issues/GEM5-331 claims broke
Ruby checkpointing on MOESI_hammer):
Outcome: "panic: Runtime Error at MESI_Three_Level-L0cache.sm:249:
Invalid RubyRequestType." This is the correct outcome because
MESE_Three_Level does have flush operations which are needed to create
checkpoints.

Checkpoint run: without --ruby
Restore run: --ruby --cpu-type DerivO3CPU
Outcome: gem5 crashes with: build/ARM/sim/port.hh:131: void
Port::takeOverFrom(Port*): Assertion `old->isConnected()' failed.

Checkpoint run: without --ruby
Restore run: --ruby --cpu-type DerivO3CPU --restore-with-cpu DerivO3CPU
Outcome: works

Checkpoint run on a C hello world without m5ops: --fast-forward 1000
--ruby --cpu-type DerivO3CPU --restore-with-cpu DerivO3CPU
Outcome: build/ARM/sim/port.hh:131: void Port::takeOverFrom(Port*):
Assertion `old->isConnected()' failed.

== MOESI_hammer build

Same as MESI_Three_Level, except that the checkpoint with --ruby works
before bb94296373dde1d0ce971ee58ad111f4225c425e as expected.

On 2/12/20 9:45 AM, Carlos Escuin wrote:

Thank you for replying,


Yes, it seems that something is not going well while switching from
AtomicSimpleCPU to DerivO3CPU.


Carlos

On 11/2/20 21:48, Giacomo Travaglini wrote:

Seems like there is an issue when you are switching over the new cpu
model.
Will have a look into that

Giacomo

 


*From:* gem5-users  on behalf of Carlos
Escuin 
*Sent:* 11 February 2020 16:46
*To:* gem5-users@gem5.org 
*Subject:* [gem5-users] ARM DerivO3CPU assertion failed
Hi all,


I'm trying to execute bzip2 spec 2006 benchmark in ARM, se, DerivO3CPU,
ruby, fast-forward.

Anyone has any idea why I'm getting this assertion failing?


Thank you,

Carlos


OUTPUT:



command line: gem5/build/ARM_MOESI_CMP_directory/gem5.opt -v
--outdir=gem5/m5out/spec2k6/bzip2_base gem5/configs/example/se.py
--num-cpus=1 --cmd=CPU2006_ARM/bzip2_dir/bzip2 --input= --output=
'--options=CPU2006_ARM/bzip2_dir/input.source 280'
--fast-forward=500 --maxinsts=1200 --cpu-type=DerivO3CPU --ruby
--l1d_size=32kB --l1i_size=32kB --l1d_assoc=8 --l1i_assoc=8
--l2_size=1MB --l2_assoc=16 --network=garnet2.0

info: Standard input is not a terminal, disabling listeners.
Global frequency set at 1 ticks per second
warn: Sockets disabled, not accepting gdb connections
Switch at instruction count:500
info: Entering event queue @ 0.  Starting simulation...
info: Increasing stack size by one page.
Switched CPUS @ tick 2977722500
switching cpus
warn: ClockedObject: Already in the requested power state, request 
ignored

warn: User mode does not have SPSR
warn: User mode does not have SPSR
gem5.opt: build/ARM_MOESI_CMP_directory/sim/port.hh:135: void
Port::takeOverFrom(Port*): Assertion `old->isConnected()' failed.
Program aborted at tick 2977722500
--- BEGIN LIBC BACKTRACE ---
gem5/build/ARM_MOESI_CMP_directory/gem5.opt(_Z15print_backtracev+0x15)[0x1281115] 

gem5/build/ARM_MOESI_CMP_directory/gem5.opt(_Z12abortHandleri+0x36)[0x128b526] 


/lib64/libpthread.so.0(+0xf7e0)[0x2afcc8dfd7e0]
/lib64/libc.so.6(gsignal+0x35)[0x2afcc99ea4f5]
/lib64/libc.so.6(abort+0x175)[0x2afcc99ebcd5]
/lib64/libc.so.6(+0x2b66e)[0x2afcc99e366e]
/lib64/libc.so.6(__assert_perror_fail+0x0)[0x2afcc99e3730]
gem5/build/ARM_MOESI_CMP_directory/gem5.opt(_ZN7BaseCPU19updateCycleCountersENS_8CPUStateE+0x0)[0x10557f0] 

gem5/build/ARM_MOESI_CMP_directory/gem5.opt(_Z

[gem5-users] Cache coherence modelling in GEm5/Ruby

[Javed Osmany]

Hi

I want to start modelling  a multicore architecture in GEM5/Ruby to explore 
cache coherence protocols.

Currently I want to model snoop based coherence protocol - Is this supported in 
Ruby?

Also, any pointers to get started on the cache coherence modelling in GEM5/Ruby 
would be much appreciated.

Best regards

JO

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Re: [gem5-users] Cache coherence modelling in GEm5/Ruby

[Daniel Gerzhoy]

Look here at the learning gem5 section on the website. There's a subsection
all about cache coherence that does a great job of explaining it.

http://www.gem5.org/documentation/learning_gem5/introduction/

On Fri, Feb 28, 2020 at 6:49 AM Javed Osmany 
wrote:

> Hi
>
>
>
> I want to start modelling  a multicore architecture in GEM5/Ruby to
> explore cache coherence protocols.
>
>
>
> Currently I want to model snoop based coherence protocol – Is this
> supported in Ruby?
>
>
>
> Also, any pointers to get started on the cache coherence modelling in
> GEM5/Ruby would be much appreciated.
>
>
>
> Best regards
>
>
>
> JO
>
>
> ___
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Re: [gem5-users] Cache coherence modelling in GEm5/Ruby

[Javed Osmany]

Thank you for the pointer.

From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Daniel 
Gerzhoy
Sent: 28 February 2020 13:58
To: gem5 users mailing list 
Subject: Re: [gem5-users] Cache coherence modelling in GEm5/Ruby

Look here at the learning gem5 section on the website. There's a subsection all 
about cache coherence that does a great job of explaining it.

http://www.gem5.org/documentation/learning_gem5/introduction/

On Fri, Feb 28, 2020 at 6:49 AM Javed Osmany 
mailto:javed.osm...@huawei.com>> wrote:
Hi

I want to start modelling  a multicore architecture in GEM5/Ruby to explore 
cache coherence protocols.

Currently I want to model snoop based coherence protocol – Is this supported in 
Ruby?

Also, any pointers to get started on the cache coherence modelling in GEM5/Ruby 
would be much appreciated.

Best regards

JO

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Re: [gem5-users] Making memory address ranges visible as NUMA nodes to the OS

[Jason Lowe-Power]

Hi Ben,

This is a great question! To be honest, I don't know the answer. I think it
will have something to do with the E820 entries in the config file, but I
don't know exactly how to do it. See this issue about trying to create a
more realistic memory layout for Linux:
https://gem5.atlassian.net/browse/GEM5-11.

Let us know if you figure anything out! Feel free to comment on that issue
or the sub tasks.

Cheers,
Jason

On Thu, Feb 27, 2020 at 8:35 AM Ben Perach  wrote:

> Hi all,
>
> I am trying to create a multicore system with two memory types, one is a
> regular DRAM and the other memory has a longer latency. The memories are
> located on different memory channels but have the same interconnect
> latency, the only latency difference is between the memory controller and
> the memory itself due to memory technology. The address range of each
> memory is continues and not interleaved. (This is something like a
> multicore system with DRAM and persistent memory).
>
> In order to be able to assign pages specifically to each memory, I want
> the OS to recognize the two memories as two different NUMA nodes.
> How can I make gem5 fs to report to the OS  that the two memory address
> ranges belong to different NUMA nodes?
> Can I add some component to the configuration script to make this happen?
> Do I need to change the BIOS somehow?
>
> (I have tried using the numa=fake tool on Linux, but it did not create new
> fake nodes.)
>
> Thank you very much,
> Ben Perach
> ___
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Re: [gem5-users] Making memory address ranges visible as NUMA nodes to the OS

[Dr. Matthias Jung]

Hi Ben,

We have a similar setup, I could bring you in contact with some people here.

Greetings,
Matthias 

--

Dr.-Ing. Matthias Jung
Expert „Virtual Hardware Engineering“
Embedded Systems Engineering
Fraunhofer IESE
Fraunhofer-Platz 1 | 67663 Kaiserslautern | Germany
Phone: +49 631 / 6800 - 2279 | Fax: +49 631 / 6800 - 9 2279
Mobile: +49 151 / 15672508
www.iese.fraunhofer.de
Email: matthias.j...@iese.fraunhofer.de

> Am 28.02.2020 um 17:38 schrieb Jason Lowe-Power :
> 
> 
> Hi Ben,
> 
> This is a great question! To be honest, I don't know the answer. I think it 
> will have something to do with the E820 entries in the config file, but I 
> don't know exactly how to do it. See this issue about trying to create a more 
> realistic memory layout for Linux: https://gem5.atlassian.net/browse/GEM5-11.
> 
> Let us know if you figure anything out! Feel free to comment on that issue or 
> the sub tasks.
> 
> Cheers,
> Jason
> 
>> On Thu, Feb 27, 2020 at 8:35 AM Ben Perach  wrote:
>> Hi all,
>> 
>> I am trying to create a multicore system with two memory types, one is a 
>> regular DRAM and the other memory has a longer latency. The memories are 
>> located on different memory channels but have the same interconnect latency, 
>> the only latency difference is between the memory controller and the memory 
>> itself due to memory technology. The address range of each memory is 
>> continues and not interleaved. (This is something like a multicore system 
>> with DRAM and persistent memory).
>> 
>> In order to be able to assign pages specifically to each memory, I want the 
>> OS to recognize the two memories as two different NUMA nodes.
>> How can I make gem5 fs to report to the OS  that the two memory address 
>> ranges belong to different NUMA nodes?
>> Can I add some component to the configuration script to make this happen?
>> Do I need to change the BIOS somehow?
>> 
>> (I have tried using the numa=fake tool on Linux, but it did not create new 
>> fake nodes.)
>> 
>> Thank you very much,
>> Ben Perach
>> ___
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Re: [gem5-users] Making memory address ranges visible as NUMA nodes to the OS

[Jason Lowe-Power]

Hey Matthias,

It would be great if we could get an example config checked into gem5! This
is a common thing that many of us are working on :).

Cheers,
Jason

On Fri, Feb 28, 2020 at 10:44 AM Dr. Matthias Jung 
wrote:

> Hi Ben,
>
> We have a similar setup, I could bring you in contact with some people
> here.
>
> Greetings,
> Matthias
>
> --
>
> Dr.-Ing. Matthias Jung
> Expert „Virtual Hardware Engineering“
> Embedded Systems Engineering
> Fraunhofer IESE
> Fraunhofer-Platz 1 | 67663 Kaiserslautern | Germany
> Phone: +49 631 / 6800 - 2279 <+49%20631%20/%206800%20-%202279> | Fax: +49
> 631 / 6800 - 9 2279 <+49%20631%20/%206800%20-%209%202279>
> Mobile: +49 151 / 15672508
> www.iese.fraunhofer.de
> Email: matthias.j...@iese.fraunhofer.de
>
> Am 28.02.2020 um 17:38 schrieb Jason Lowe-Power :
>
> 
> Hi Ben,
>
> This is a great question! To be honest, I don't know the answer. I think
> it will have something to do with the E820 entries in the config file, but
> I don't know exactly how to do it. See this issue about trying to create a
> more realistic memory layout for Linux:
> https://gem5.atlassian.net/browse/GEM5-11.
>
> Let us know if you figure anything out! Feel free to comment on that issue
> or the sub tasks.
>
> Cheers,
> Jason
>
> On Thu, Feb 27, 2020 at 8:35 AM Ben Perach  wrote:
>
>> Hi all,
>>
>> I am trying to create a multicore system with two memory types, one is a
>> regular DRAM and the other memory has a longer latency. The memories are
>> located on different memory channels but have the same interconnect
>> latency, the only latency difference is between the memory controller and
>> the memory itself due to memory technology. The address range of each
>> memory is continues and not interleaved. (This is something like a
>> multicore system with DRAM and persistent memory).
>>
>> In order to be able to assign pages specifically to each memory, I want
>> the OS to recognize the two memories as two different NUMA nodes.
>> How can I make gem5 fs to report to the OS  that the two memory address
>> ranges belong to different NUMA nodes?
>> Can I add some component to the configuration script to make this happen?
>> Do I need to change the BIOS somehow?
>>
>> (I have tried using the numa=fake tool on Linux, but it did not create
>> new fake nodes.)
>>
>> Thank you very much,
>> Ben Perach
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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[gem5-users] Develop branch on github

[Abhishek Singh]

Hello Everyone,

Is there a way I can access develop branch on github?
In the branches option and tag option, I can not find it.

Also, on google what is this branch "feature-gcn3-model

"?




Best regards,

Abhishek
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Re: [gem5-users] Develop branch on github

[Bobby Bruce]

Abhishek,

It appears the develop branch is not being properly mirrored correctly to
GitHub. I'll work to fix this today. Thanks for bringing this to my
attention.

The feature-gnc3-branch is for the development of a new feature relating to
the AMD GCN3 ISA architecture. It will be merged to the develop branch at a
later date.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Feb 28, 2020 at 11:58 AM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hello Everyone,
>
> Is there a way I can access develop branch on github?
> In the branches option and tag option, I can not find it.
>
> Also, on google what is this branch "feature-gcn3-model
> 
> "?
>
>
>
>
> Best regards,
>
> Abhishek
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Re: [gem5-users] Develop branch on github

[Abhishek Singh]

Hello Bobby,

Thank you for taking care of this.

Best regards,

Abhishek


On Fri, Feb 28, 2020 at 3:13 PM Bobby Bruce  wrote:

> Abhishek,
>
> It appears the develop branch is not being properly mirrored correctly to
> GitHub. I'll work to fix this today. Thanks for bringing this to my
> attention.
>
> The feature-gnc3-branch is for the development of a new feature relating
> to the AMD GCN3 ISA architecture. It will be merged to the develop branch
> at a later date.
>
> Kind regards,
> Bobby
> --
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Fri, Feb 28, 2020 at 11:58 AM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Everyone,
>>
>> Is there a way I can access develop branch on github?
>> In the branches option and tag option, I can not find it.
>>
>> Also, on google what is this branch "feature-gcn3-model
>> 
>> "?
>>
>>
>>
>>
>> Best regards,
>>
>> Abhishek
>> ___
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>
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Re: [gem5-users] Develop branch on github

[Bobby Bruce]

The gem5 git repo ( https://github.com/gem5/gem5 ) is now properly mirrored!

--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Feb 28, 2020 at 12:15 PM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hello Bobby,
>
> Thank you for taking care of this.
>
> Best regards,
>
> Abhishek
>
>
> On Fri, Feb 28, 2020 at 3:13 PM Bobby Bruce  wrote:
>
>> Abhishek,
>>
>> It appears the develop branch is not being properly mirrored correctly to
>> GitHub. I'll work to fix this today. Thanks for bringing this to my
>> attention.
>>
>> The feature-gnc3-branch is for the development of a new feature relating
>> to the AMD GCN3 ISA architecture. It will be merged to the develop branch
>> at a later date.
>>
>> Kind regards,
>> Bobby
>> --
>> Dr. Bobby R. Bruce
>> Room 2235,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>>
>> web: https://www.bobbybruce.net
>>
>>
>> On Fri, Feb 28, 2020 at 11:58 AM Abhishek Singh <
>> abhishek.singh199...@gmail.com> wrote:
>>
>>> Hello Everyone,
>>>
>>> Is there a way I can access develop branch on github?
>>> In the branches option and tag option, I can not find it.
>>>
>>> Also, on google what is this branch "feature-gcn3-model
>>> 
>>> "?
>>>
>>>
>>>
>>>
>>> Best regards,
>>>
>>> Abhishek
>>> ___
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>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
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[gem5-users] Fw: Fw: Asim benchmarks on gem5

[ABD ALRHMAN ABO ALKHEEL]

Hi All,

I have run the following command but the rcS script is not working. Any help 
would be appreciated.


The output on system.terminal

ALSA device list:
  No soundcards found.
input: AT Raw Set 2 keyboard as 
/devices/smb.14/motherboard.15/iofpga.17/1c06.kmi/serio0/input/input0
input: touchkitPS/2 eGalax Touchscreen as 
/devices/smb.14/motherboard.15/iofpga.17/1c07.kmi/serio1/input/input2
EXT2-fs (sda1): warning: mounting unchecked fs, running e2fsck is recommended
VFS: Mounted root (ext2 filesystem) on device 8:1.
Freeing unused kernel memory: 292K (806d1000 - 8071a000)
init: cannot open '/initlogo.rle'
init: cannot find '/system/etc/install-recovery.sh', disabling 'flash_recovery'
init: using deprecated syntax for specifying property 'persist.sys.usb.config', 
use ${name} instead
init: using deprecated syntax for specifying property 'sys.usb.config', use 
${name} instead
init: using deprecated syntax for specifying property 'sys.usb.config', use 
${name} instead
random: servicemanager urandom read with 19 bits of entropy available
/system/bin/sh: No controlling tty: open /dev/tty: No such device or address
/system/bin/sh: warning: won't have full job control
root@android:/ # init: untracked pid 979 exited




I used this command:

./build/ARM/gem5.opt configs/example/fs.py --cpu-type=AtomicSimpleCPU 
--mem-type=SimpleMemory --machine-type=VExpress_EMM --os-type=android-ics 
--kernel=/home/abdkhail/gem5/full_system_images/binaries/vmlinux.vexpress_emm.20170616
 
--disk-image=/home/abdkhail/gem5/full_system_images/disks/ARMv7a-ICS-Android.SMP.Asimbench-v3.img
 
--dtb-filename=/home/abdkhail/gem5/full_system_images/binaries/vexpress-v2p-ca15-tc1-gem5_1cpus.20170616.dtb
 --mem-size=1800MB -n 1 
--script=/home/abdkhail/gem5/full_system_images/asimbench_boot_scripts/test.rcS

The test.rcS
#!/bin/sh


echo "Starting sfw test..."

/sbin/m5 resetstats

echo "HI"

/sbin/m5 dumpstats

echo "finished sfw test, exiting..."

/sbin/m5 exit
/sbin/m5 exit

From: gem5-users  on behalf of ABD ALRHMAN ABO 
ALKHEEL 
Sent: Tuesday, February 25, 2020 4:24:53 PM
To: Ciro Santilli ; gem5 users mailing list 
; gem5-users 
Subject: Re: [gem5-users] Fw: Asim benchmarks on gem5

Hi All,

I have run the following command but the rcS script is not working. Any help 
would be appreciated.


The output on system.terminal

ALSA device list:
  No soundcards found.
input: AT Raw Set 2 keyboard as 
/devices/smb.14/motherboard.15/iofpga.17/1c06.kmi/serio0/input/input0
input: touchkitPS/2 eGalax Touchscreen as 
/devices/smb.14/motherboard.15/iofpga.17/1c07.kmi/serio1/input/input2
EXT2-fs (sda1): warning: mounting unchecked fs, running e2fsck is recommended
VFS: Mounted root (ext2 filesystem) on device 8:1.
Freeing unused kernel memory: 292K (806d1000 - 8071a000)
init: cannot open '/initlogo.rle'
init: cannot find '/system/etc/install-recovery.sh', disabling 'flash_recovery'
init: using deprecated syntax for specifying property 'persist.sys.usb.config', 
use ${name} instead
init: using deprecated syntax for specifying property 'sys.usb.config', use 
${name} instead
init: using deprecated syntax for specifying property 'sys.usb.config', use 
${name} instead
random: servicemanager urandom read with 19 bits of entropy available
/system/bin/sh: No controlling tty: open /dev/tty: No such device or address
/system/bin/sh: warning: won't have full job control
root@android:/ # init: untracked pid 979 exited




I used this command:

./build/ARM/gem5.opt configs/example/fs.py --cpu-type=AtomicSimpleCPU 
--mem-type=SimpleMemory --machine-type=VExpress_EMM --os-type=android-ics 
--kernel=/home/abdkhail/gem5/full_system_images/binaries/vmlinux.vexpress_emm.20170616
 
--disk-image=/home/abdkhail/gem5/full_system_images/disks/ARMv7a-ICS-Android.SMP.Asimbench-v3.img
 
--dtb-filename=/home/abdkhail/gem5/full_system_images/binaries/vexpress-v2p-ca15-tc1-gem5_1cpus.20170616.dtb
 --mem-size=1800MB -n 1 
--script=/home/abdkhail/gem5/full_system_images/asimbench_boot_scripts/test.rcS

The test.rcS
#!/bin/sh


echo "Starting sfw test..."

/sbin/m5 resetstats

echo "HI"

/sbin/m5 dumpstats

echo "finished sfw test, exiting..."

/sbin/m5 exit
/sbin/m5 exit

From: gem5-users  on behalf of ABD ALRHMAN ABO 
ALKHEEL 
Sent: Tuesday, February 25, 2020 5:32:56 AM
To: Ciro Santilli ; gem5 users mailing list 
; gem5-users 
Subject: Re: [gem5-users] Fw: Asim benchmarks on gem5

Hi All,

I have run the following command but the rcS script is not working. Any help 
would be appreciated.


The output on system.terminal

ALSA device list:
  No soundcards found.
input: AT Raw Set 2 keyboard as 
/devices/smb.14/motherboard.15/iofpga.17/1c06.kmi/serio0/input/input0
input: touchkitPS/2 eGalax Touchscreen as 
/devices/smb.14/motherboard.15/iofpga.17/1c07.kmi/serio1/input/input2
EXT2-fs (sda1): warning: mounting unchecked fs, running e2fsck is recommended
VFS: Mounted root (ext2 filesystem) on

Re: [gem5-users] Develop branch on github

[Abhishek Singh]

Hello Everyone and Bobby,

Are older stable versions removed from GitHub?
Is there a way to access them?


Best regards,

Abhishek


On Fri, Feb 28, 2020 at 4:44 PM Bobby Bruce  wrote:

> The gem5 git repo ( https://github.com/gem5/gem5 ) is now properly
> mirrored!
>
> --
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Fri, Feb 28, 2020 at 12:15 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hello Bobby,
>>
>> Thank you for taking care of this.
>>
>> Best regards,
>>
>> Abhishek
>>
>>
>> On Fri, Feb 28, 2020 at 3:13 PM Bobby Bruce  wrote:
>>
>>> Abhishek,
>>>
>>> It appears the develop branch is not being properly mirrored correctly
>>> to GitHub. I'll work to fix this today. Thanks for bringing this to my
>>> attention.
>>>
>>> The feature-gnc3-branch is for the development of a new feature relating
>>> to the AMD GCN3 ISA architecture. It will be merged to the develop branch
>>> at a later date.
>>>
>>> Kind regards,
>>> Bobby
>>> --
>>> Dr. Bobby R. Bruce
>>> Room 2235,
>>> Kemper Hall, UC Davis
>>> Davis,
>>> CA, 95616
>>>
>>> web: https://www.bobbybruce.net
>>>
>>>
>>> On Fri, Feb 28, 2020 at 11:58 AM Abhishek Singh <
>>> abhishek.singh199...@gmail.com> wrote:
>>>
 Hello Everyone,

 Is there a way I can access develop branch on github?
 In the branches option and tag option, I can not find it.

 Also, on google what is this branch "feature-gcn3-model
 
 "?




 Best regards,

 Abhishek
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