[gem5-users] Running a program with spin lock under the ARM architecture gets the wrong result

[Chao Fu via gem5-users]

Hi,
 Recently I ran a program which has spin lock(I did it myself using atomic 
operations) under ARM architecture on gem5, but I found that the result was not 
as expected!  I ran this program on a physical machine with arm64 and the 
result is right. Also, I compiled the same source code with x86 ISA, and the 
result is also right on GEM5. So I guess maybe there are some wrong with GEM5 
source code or maybe I'm compiling it the wrong way?(I tried both full system 
mode and system call mode, but I did not get the right results either)

Here is my running log:

gem5 executing on ubuntu, pid 23488
command line: build/ARM_HTM/gem5.debug configs/example/se.py 
--cpu-type=O3_ARM_v7a_3 --num-cpus=4 --ruby --cmd=benchmark/arm-lock

Global frequency set at 1 ticks per second
 REAL SIMULATION 
Parallel histogram with 4 procs
Hello from thread 0
Hello from thread 1
Hello from thread 3
Hello from thread 2
Goodbye from thread 0
Goodbye from thread 1
Goodbye from thread 3
Goodbye from thread 2
2 seconds
Total is 2943
Expected total is 4000
Exiting @ tick 187329500 because exiting with last active thread context

Here is my program source code:

#include 
#include 
#include 
#include 
#include 
#include 
#include 

#define ARRAYSIZE 2
#define ITERATIONS1000

// spin lock
typedef atomic_int lock_t;

void lock_init(lock_t *lock) {
atomic_init(lock, 0);
}

void lock_acquire(lock_t *lock) {
while (atomic_exchange_explicit(lock, 1, memory_order_acquire))
; // spin until acquired
}

int lock_is_acquired(lock_t *lock) {
return atomic_load_explicit(lock, memory_order_acquire);
}

void lock_release(lock_t *lock) {
atomic_store_explicit(lock, 0, memory_order_release);
}

volatile long int histogram[ARRAYSIZE];
lock_t global_lock;

void* work(void* void_ptr) {
// Use thread id for RNG seed,
// this will prevent threads generating the same array indices.
long int idx = (long int)void_ptr;
unsigned int seedp = (unsigned int)idx;
int i, rc;

printf("Hello from thread %ld\n", idx);

for (i=0; i

[gem5-users] Page crossing prefetch

[Rayaroth Kunnummal, Rejith via gem5-users]

Hi,
Has anyone looked at enabling page crossing prefetch in Gem5? I see the 
below code where it says ignoring the page crossing prefetch if the new address 
is not in the same page.


} else {

DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");

}


Thanks,

Rejith

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[gem5-users] Re: how to add more than 1 ide disk in gem5 fullsystem

[Ayaz Akram via gem5-users]

Hi,

I think the config script (system.py) in boot tests on gem5-resources (
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/boot-exit/configs/)
shows how to add two disks in your configuration. Specifically, looking
into setDiskImages()might be helpful.

-Ayaz

On Tue, Nov 24, 2020 at 8:35 AM Liyichao via gem5-users 
wrote:

>
> hi all：
>  how to add more than 1 ide disks in gem5 fullsystem？
>
>
> I want to see that sda sdb sdc ... in OS so that I can test some 
> distribution application like ceph.
>
>
>
> --
>
> 李翼超 charlie
> Mobile：+86-15858232899
> Email：liyic...@huawei.com
>
>
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[gem5-users] Re: Instruction execute stage clock cycles in MinorCPU

[Ayaz Akram via gem5-users]

Yeah, it does not seem like m5ops are implemented in RISC-V yet. I did not
see any RISC-V specific code in "util/m5/src/abi/". One workaround could be
to stop simulation at a particular instruction count (e.g. if you know at
what instruction number your function of interest starts and ends) from the
Python run script and dump stats. Please, note that there might be other
(and better) ways to do this.

-Ayaz

On Wed, Nov 25, 2020 at 9:37 PM Volkan Mutlu via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Ayaz,
>
> Thank you so much for your answers, these definitely cleared things up a
> bit. I'll try to look deeper in the code and see if I can navigate the
> Python interface to adjust latencies. Also thanks for pointing out m5ops, I
> was not aware. Though I wonder whether the documentation has not been
> updated or if RISC-V has not been provided as a target ISA option for this
> yet, I'll check that out as well.
>
> Best,
> Volkan
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