[gem5-users] Re: Flushing the Caches

[Samuel Thomas via gem5-users]

Hi Sherif and Arth,

I had a similar problem. I resolved it by coming up with a somewhat hacky 
solution that utilizes the “forEachBlk” function call in the base tags. For 
context, I needed the main memory state to be consistent between a task running 
some component on both big and little CPU clusters in the ARM bigLITTLE 
configurations, so a lazy eviction protocol (such as invalidating cache blocks) 
wasn’t sufficient.

In src/mem/cache/tags/base.cc , add the following public 
function.

void
BaseTags::flushAll(const char *parentName)
{
auto blk_flush = [&parentName](CacheBlk &blk) {
Cache *parent = 
dynamic_cast(SimObject::find(parentName));
if (blk.isValid() && blk.isDirty()) {
parent->evictBlk(&blk);
}
};
forEachBlk(blk_flush);
}

Then, in src/mem/cache.cc , you can add

void
Cache::flush()
{
tags->flushAll(name().c_str());
}

As you can tell, this is a very quick and dirty solution, so if there exists a 
better way to do this, I would also greatly appreciate and benefit from it!

Best,
Sam

> On Mar 29, 2021, at 12:46 PM, ARTHUR PERAIS via gem5-users 
>  wrote:
> 
> Hi Sherif,
> 
> Maybe the functionality is already there, but it may not be as easy as it 
> sounds depending on what you mean by "flushing". Functionally invalidating 
> cache lines is staightforward, but anything that is dirty in the cache should 
> be written back, and this may be harder to handle especially if you want 
> timing, not just functionality. If I had to start somewhere, I would see how 
> back invalidations are handled (invalidation of L1 line because line is 
> evicted from L2 and L2 is inclusive of L1) and apply the same process on 
> dirty line sequentially.ur
> 
> Maybe more context would be helpful :)
> 
> Arth
> 
> De: "gem5 users mailing list" 
> À: "gem5 users mailing list" 
> Cc: "Sherif AbdelFadil" 
> Envoyé: Lundi 29 Mars 2021 10:45:12
> Objet: [gem5-users] Flushing the Caches
> 
> Hi,
> I was wondering if someone already implemented the functionality of flushing 
> all caches in gem5. It seems relatively simple to implement and I imagine it 
> would be useful in a lot of cases, yet I couldn't find anything online.
> 
> Regards,
> Sherif
> 
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[gem5-users] Re: Flushing the Caches

[ARTHUR PERAIS via gem5-users]

Hi Sherif, 

Maybe the functionality is already there, but it may not be as easy as it 
sounds depending on what you mean by "flushing". Functionally invalidating 
cache lines is staightforward, but anything that is dirty in the cache should 
be written back, and this may be harder to handle especially if you want 
timing, not just functionality. If I had to start somewhere, I would see how 
back invalidations are handled (invalidation of L1 line because line is evicted 
from L2 and L2 is inclusive of L1) and apply the same process on dirty line 
sequentially.ur 

Maybe more context would be helpful :) 

Arth 


De: "gem5 users mailing list"  
À: "gem5 users mailing list"  
Cc: "Sherif AbdelFadil"  
Envoyé: Lundi 29 Mars 2021 10:45:12 
Objet: [gem5-users] Flushing the Caches 

Hi, 
I was wondering if someone already implemented the functionality of flushing 
all caches in gem5. It seems relatively simple to implement and I imagine it 
would be useful in a lot of cases, yet I couldn't find anything online. 

Regards, 
Sherif 

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[gem5-users] Re: ISSUES FACING WHILE INTEGRATING GEM5 AND DRAMSIM3

[Kodali, Monica Bhargavi via gem5-users]

Ok thank you
Best regards,
Monica Bhargavi Kodali.

Get Outlook for Android


From: Mahyar Samani via gem5-users 
Sent: Monday, March 29, 2021 12:23:00 PM
To: gem5 users mailing list 
Cc: hauru...@gmail.com ; Mahyar Samani 
Subject: [gem5-users] Re: ISSUES FACING WHILE INTEGRATING GEM5 AND DRAMSIM3

[External Email]
Hello,

I would say overall DRAMSim3 is more accurate and to be honest it is much 
easier to use than DRAMSim2. I am also doing an evaluation on memory models 
between DRAMSim3 and gem5, based on the current results I would suggest you use 
either DRAMSim3 (using the temporary solution I proposed) or gem5 models.

Best Regards,

On Sun, Mar 28, 2021 at 7:23 AM haurunis--- via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi Mahyar,

Sorry to bother but I would like to ask a related question:
So for better DRAM power/timing simulation, will DRAMSim3 be the best among 
DRAMCtrl (gem5-prebuilt) and DRAMSim2? The reason I am asking is that I also 
tried to get DRAMSim2 to work in gem5. However, following the 
/ext/DRAMSim2/readme, I kept running into
```command line: build/X86/gem5.opt configs/example/se.py -c 
tests/test-progs/hello/bin/x86/linux/hello --cpu-type=TraceCPU --caches 
--l2cache --mem-type=dramsim2

Usage: se.py [options]

se.py: error: option --mem-type: invalid choice:
```
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--
Mahyar Samani (he/him/his)
Electrical and Computer Engineering Department
Research Assistant at 
DArchR
 (2235 Kemper Hall)
Secretary
ECE-GSA
Vice President
Iranian Student Association at UC Davis
University of California, Davis
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[gem5-users] Re: ISSUES FACING WHILE INTEGRATING GEM5 AND DRAMSIM3

[Mahyar Samani via gem5-users]

Hello,

I would say overall DRAMSim3 is more accurate and to be honest it is much
easier to use than DRAMSim2. I am also doing an evaluation on memory models
between DRAMSim3 and gem5, based on the current results I would suggest you
use either DRAMSim3 (using the temporary solution I proposed) or gem5
models.

Best Regards,

On Sun, Mar 28, 2021 at 7:23 AM haurunis--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Mahyar,
>
> Sorry to bother but I would like to ask a related question:
> So for better DRAM power/timing simulation, will DRAMSim3 be the best
> among DRAMCtrl (gem5-prebuilt) and DRAMSim2? The reason I am asking is that
> I also tried to get DRAMSim2 to work in gem5. However, following the
> /ext/DRAMSim2/readme, I kept running into
> ```command line: build/X86/gem5.opt configs/example/se.py -c
> tests/test-progs/hello/bin/x86/linux/hello --cpu-type=TraceCPU --caches
> --l2cache --mem-type=dramsim2
>
> Usage: se.py [options]
>
> se.py: error: option --mem-type: invalid choice:
> ```
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-- 
Mahyar Samani (he/him/his)
Electrical and Computer Engineering Department
Research Assistant at *DArchR  (*2235 Kemper
Hall)
Secretary
ECE-GSA
Vice President
Iranian Student Association at UC Davis
University of California, Davis
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[gem5-users] Re: Problem with SimpleCache provided by learning_gem5/part2 when the ISA is ARM

[Jason Lowe-Power via gem5-users]

Hi Fugelin,

This is an interesting bug! I would guess that there's a packet being
copied in the cache when it should be reused. The simple cache isn't tested
with Arm, and it's really just an example and shouldn't be used for
anything "real". If you do figure out the bug, we'd love to accept your
contribution!

Cheers,
Jason

On Tue, Mar 23, 2021 at 8:48 PM Gelin Fu via gem5-users 
wrote:

> Hi all,
>
> I am a freshman about gem5, so I try the learing_gem5 tutorial first. When
> I was modeling SimpleCache in the tutorial part2, I find this model can
> only work well with X86, not ARM. The screen outputs as follows:
> gem5 version 20.1.0.4
> gem5 compiled Mar 24 2021 11:38:19
> gem5 started Mar 24 2021 11:40:55
> gem5 executing on fgl-virtual-machine, pid 46006
> command line: build/ARM/gem5.opt configs/tutorials/simple_cache.py
>
> warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
> warn: membus.master is deprecated. `master` is now called
> `mem_side_ports`
> warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
> Global frequency set at 1 ticks per second
> warn: No dot file generated. Please install pydot to generate the dot
> file and pdf.
> warn: DRAM device capacity (8192 Mbytes) does not match the address
> range assigned (512 Mbytes)
> 0: system.remote_gdb: listening for remote gdb on port 7000
> warn: CoherentXBar system.membus has no snooping ports attached!
> Beginning simulation!
> info: Entering event queue @ 0.  Starting simulation...
> gem5.opt: build/ARM/mem/request.hh:776: uint64_t
> Request::getExtraData() const: Assertion
> `privateFlags.isSet(VALID_EXTRA_DATA)' failed.
> Program aborted at tick 12055000
>
> I would like to know if this SimpleCache object can be used for the ARM
> ISA or the reason why it cannot be used for ARM  ISA.
>
> Thanks and regards
> Fugelin
>  Xi'an Jiaotong University
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[gem5-users] Flushing the Caches

[Sherif AbdelFadil via gem5-users]

Hi,
I was wondering if someone already implemented the functionality of
flushing all caches in gem5. It seems relatively simple to implement and I
imagine it would be useful in a lot of cases, yet I couldn't find anything
online.

Regards,
Sherif
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