[gem5-users] Re: Can't define my own create() function

[weiwei Zhao via gem5-users]

Yes, I saw your template for dummyxx, and I add a dummy  parameter to my 
constructor ,it doesn;t compile error.
Thank you
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[gem5-users] Re: Can't define my own create() function

[Gabe Black via gem5-users]

Hi. The automatically generated create() method will only exist if your
SimObject can be constructed with a constant reference to the parameter
type. Or in other words, if it has a constructor of the form
TraceManager(const TraceManagerParams ¶ms). You can disable that by
just adding a dummy parameter like an int which you don't have to use for
anything. This is somewhat like how c++ operator overloading disambiguates
the i++ and the ++i cases.

Gabe

On Fri, Apr 9, 2021 at 7:11 PM weiwei Zhao via gem5-users <
gem5-users@gem5.org> wrote:

> The compile error like this:
>
> build/ARM/params/TraceManager.do: In function
> `TraceManagerParams::create() const':
> /data1/zhaoweiwei/gem5/base_v21.0.0.0/build/ARM/params/TraceManager.cc:53:
> multiple definition of `TraceManagerParams::create() const'
> build/ARM/sim/tracemanager.do:/data1/zhaoweiwei/gem5/base_v21.0.0.0/build/ARM/sim/tracemanager.cc:156:
> first defined here
> collect2: error: ld returned 1 exit status
> scons: *** [build/ARM/gem5.debug] Error 1
> scons: building terminated because of errors.
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[gem5-users] Re: Can't define my own create() function

[weiwei Zhao via gem5-users]

The compile error like this:

build/ARM/params/TraceManager.do: In function `TraceManagerParams::create() 
const':
/data1/zhaoweiwei/gem5/base_v21.0.0.0/build/ARM/params/TraceManager.cc:53: 
multiple definition of `TraceManagerParams::create() const'
build/ARM/sim/tracemanager.do:/data1/zhaoweiwei/gem5/base_v21.0.0.0/build/ARM/sim/tracemanager.cc:156:
 first defined here
collect2: error: ld returned 1 exit status
scons: *** [build/ARM/gem5.debug] Error 1
scons: building terminated because of errors.
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[gem5-users] Can't define my own create() function

[weiwei.zhao via gem5-users]

Hello ,
I am now upgrade gem5 to v21, and I encounter a compile error which say I 
multidefine  the create function.


I find Gem5 has a new patch to remove unnecessary create function:
 https://gem5-review.googlesource.com/c/public/gem5/+/35942
https://gem5-review.googlesource.com/c/public/gem5/+/36536/2

I want ask how to keep my create() function, becuase I need define my own 
create function in my SimObject.

Thank you
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[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

[Giacomo Travaglini via gem5-users]

Hi Wenqi

> -Original Message-
> From: wq...@utexas.edu 
> Sent: 09 April 2021 23:07
> To: Giacomo Travaglini ; gem5 users mailing
> list 
> Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU
>
> Hi Giacomo,
>
> Thanks for letting me know what the problem is, I am able to verify the
> solution on my end as well :-)
>
> Just curious, as I am not familiar with the arm system, do you always need to
> provide a separate bootloader to boot arm FS simulation in gem5?

You don't if you run a baremetal workload in an arm FS simulation.
If you boot an OS like Linux, then the answer is: it depends, but you need to 
initialize the system somehow.

The default behaviour in fs_bigLITTLE, fs and fs_starter is to use the gem5 
bootloader (very minimal) to boot the OS.
Nothing stops you from using different kinds of bootloaders though. For example 
in the past I have used the aarch64 bootwrapper which
is generating a single image with kernel + bootloader (external) + dtb. Lately 
I have been using GRUB as well.

You could in theory avoid having the extra bootloader binary; one option is to 
embed it in gem5 (I might be wrong but I believe this is what QEMU does), and 
the other is to initialize the platform
on the host side (replicating what the guest bootloader is supposed to do 
before starting executing the kernel). Those two options are currently not 
supported.

> Will the one packed with the kernel work? (I assume when sim x86, it uses
> the bootloader from the kernel).

I believe x86 is implementing one of the two options above

>
> Best,
>
> Wenqi

Kind Regards

Giacomo

>
> On 4/9/21 5:09 AM, Giacomo Travaglini wrote:
> > Hi Wenqi,
> >
> > I have found the problem; in order to fix it you should recompile the
> > bootloaders from system/arm/bootloader/arm64 and replace all of them
> with the ones in M5_PATH/binaries That solves the problem on my side.
> >
> > I am gonna update the guest binaries tarball in gem5.org (I was going
> > to do that anyway after the 21.0 release)
> >
> > Kind Regards
> >
> > Giacomo
> >
> >
> >> -Original Message-
> >> From: Giacomo Travaglini
> >> Sent: 07 April 2021 09:13
> >> To: Wenqi Yin ; gem5 users mailing list  >> us...@gem5.org>
> >> Subject: RE: [gem5-users] Fail to Boot Multicore Arm System with KVM
> >> CPU
> >>
> >> Thanks Wenqi,
> >>
> >> I was about to suggest the same; please feel free to open a JIRA ticket at:
> >>
> >> https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/
> >>
> >> Kind Regards
> >>
> >> Giacomo
> >>
> >>> -Original Message-
> >>> From: Wenqi Yin 
> >>> Sent: 07 April 2021 06:40
> >>> To: gem5 users mailing list 
> >>> Cc: Giacomo Travaglini 
> >>> Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM
> >>> CPU
> >>>
> >>> Hi All,
> >>>
> >>> The problem turns out to be with the recent release v21.0. I rolled
> >>> back to v20.2, it can boot 8+ KVM cpu after applying all the changes
> >> discusses before.
> >>> Shall I report this issue anywhere? If so is there any instructions to do 
> >>> so?
> >>> Thanks
> >>>
> >>> Best,
> >>> Wenqi
> >>>
>  On Apr 6, 2021, at 11:54, wq...@utexas.edu wrote:
> 
>  Hi Giacomo,
> 
>  I pasted the perhaps most relevant dmesg output of guest kernel and
>  the
> >>> disassembled dtb file snippet (In this case, I use fs_bigLittle.py
> >>> and boot 4
> >>> vCPU) . Also attached the full dts and dmesg output in case I left
> anything.
>  [0.00] CPU features: GIC system register CPU interface present
> but
> >>> disab
>  led by higher exception level
> 
>  [0.052000] smp: Bringing up secondary CPUs ...
>  [2.004021] random: fast init done
>  [2.132023] CPU1: failed to come online
>  [2.132023] CPU1: failed in unknown state : 0x0
>  [4.244045] CPU2: failed to come online
>  [4.244045] CPU2: failed in unknown state : 0x0
>  [6.356068] CPU3: failed to come online
>  [6.356068] CPU3: failed in unknown state : 0x0
>  [8.468091] CPU4: failed to come online
>  [8.468091] CPU4: failed in unknown state : 0x0
>  [8.468091] smp: Brought up 1 node, 1 CPU
> 
> 
>  cpus {
>   #address-cells = <0x1>;
>   #size-cells = <0x0>;
> 
>   cpu@0 {
>   device_type = "cpu";
>   compatible = "gem5,arm-cpu";
>   reg = <0x0>;
>   enable-method = "spin-table";
>   cpu-release-addr = <0x0 0x87f8>;
>   clock-frequency = <0x773593ff>;
>   phandle = <0xf>;
>   };
> 
>   cpu@1 {
>   device_type = "cpu";
>   compatible = "gem5,arm-cpu";
>   reg = <0x1>;
> 

[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

[wqyin--- via gem5-users]

Hi Giacomo,

Thanks for letting me know what the problem is, I am able to verify the 
solution on my end as well :-)


Just curious, as I am not familiar with the arm system, do you always 
need to provide a separate bootloader to boot arm FS simulation in gem5? 
Will the one packed with the kernel work? (I assume when sim x86, it 
uses the bootloader from the kernel).


Best,

Wenqi

On 4/9/21 5:09 AM, Giacomo Travaglini wrote:

Hi Wenqi,

I have found the problem; in order to fix it you should recompile the 
bootloaders from system/arm/bootloader/arm64 and replace all of them with the 
ones in M5_PATH/binaries
That solves the problem on my side.

I am gonna update the guest binaries tarball in gem5.org (I was going to do 
that anyway after the 21.0 release)

Kind Regards

Giacomo



-Original Message-
From: Giacomo Travaglini
Sent: 07 April 2021 09:13
To: Wenqi Yin ; gem5 users mailing list 
Subject: RE: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU

Thanks Wenqi,

I was about to suggest the same; please feel free to open a JIRA ticket at:

https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/

Kind Regards

Giacomo


-Original Message-
From: Wenqi Yin 
Sent: 07 April 2021 06:40
To: gem5 users mailing list 
Cc: Giacomo Travaglini 
Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM
CPU

Hi All,

The problem turns out to be with the recent release v21.0. I rolled
back to v20.2, it can boot 8+ KVM cpu after applying all the changes

discusses before.

Shall I report this issue anywhere? If so is there any instructions to do so?
Thanks

Best,
Wenqi


On Apr 6, 2021, at 11:54, wq...@utexas.edu wrote:

Hi Giacomo,

I pasted the perhaps most relevant dmesg output of guest kernel and
the

disassembled dtb file snippet (In this case, I use fs_bigLittle.py and
boot 4
vCPU) . Also attached the full dts and dmesg output in case I left anything.

[0.00] CPU features: GIC system register CPU interface present but

disab

led by higher exception level

[0.052000] smp: Bringing up secondary CPUs ...
[2.004021] random: fast init done
[2.132023] CPU1: failed to come online
[2.132023] CPU1: failed in unknown state : 0x0
[4.244045] CPU2: failed to come online
[4.244045] CPU2: failed in unknown state : 0x0
[6.356068] CPU3: failed to come online
[6.356068] CPU3: failed in unknown state : 0x0
[8.468091] CPU4: failed to come online
[8.468091] CPU4: failed in unknown state : 0x0
[8.468091] smp: Brought up 1 node, 1 CPU


cpus {
 #address-cells = <0x1>;
 #size-cells = <0x0>;

 cpu@0 {
 device_type = "cpu";
 compatible = "gem5,arm-cpu";
 reg = <0x0>;
 enable-method = "spin-table";
 cpu-release-addr = <0x0 0x87f8>;
 clock-frequency = <0x773593ff>;
 phandle = <0xf>;
 };

 cpu@1 {
 device_type = "cpu";
 compatible = "gem5,arm-cpu";
 reg = <0x1>;
 enable-method = "spin-table";
 cpu-release-addr = <0x0 0x87f8>;
 clock-frequency = <0x773593ff>;
 phandle = <0x10>;
 };

 cpu@2 {
 device_type = "cpu";
 compatible = "gem5,arm-cpu";
 reg = <0x2>;
 enable-method = "spin-table";
 cpu-release-addr = <0x0 0x87f8>;
 clock-frequency = <0x773593ff>;
 phandle = <0x11>;
 };

 cpu@3 {
 device_type = "cpu";
 compatible = "gem5,arm-cpu";
 reg = <0x3>;
 enable-method = "spin-table";
 cpu-release-addr = <0x0 0x87f8>;
 clock-frequency = <0x773593ff>;
 phandle = <0x12>;
 };

 cpu@104 {
 device_type = "cpu";
 compatible = "gem5,arm-cpu";
 reg = <0x104>;
 enable-method = "spin-table";
 cpu-release-addr = <0x0 0x87f8>;
 clock-frequency = <0x3b9ac9ff>;
 phandle = <0x13>;
 };
 };

best,

Wenqi

On 4/6/21 7:35 AM, Giacomo Travaglini wrote:

Hi Wenqi,

Could you provide us with the booting log of the guest kernel?

Kind Regards

Giacomo


-Original Message-
From: Wenqi Yin 
Sent: 06 April 2021 05:48
To: Giacomo Travaglini 
Cc: gem5 users mailing list ; Wenqi Yin

Subject: Re: [gem5-users] Fail to Boot Multi

[gem5-users] Converting KVM-taken checkpoint to atomic-needed checkpoint

[Majid Jalili via gem5-users]

Hi,

Is it practically possible to convert the KVM-taken checkpoint such that I
can restore it with Atomic CPU? This is particularly important because I
have to use KVM to take my checkpoints on an ARM machine and then transfer
them to my X86 cluster to run the checkpoints.
I cannot avoid KVM on ARM, because my simpoints are very long, and I cannot
continue my simulation on ARM host because it is slow and not free.
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[gem5-users] Copying/Writing data from one packet to another packet in gem5

[bagchi95aritra--- via gem5-users]

Hi all, 

In gem5, the data a packet brings from the main memory to the cache is first 
written into a particular cache block. Later, that cache block supplies the 
data to the outstanding misses at the MSHR (targets). gem5 has some built-in 
methods defined under the “Packet” class for transferring data between a cache 
block and a packet. 

Is there any way/method in gem5 by which the data of a packet can directly be 
written/copied to another packet? Can anyone put some light on it? 

Thanks and regards,
Aritra
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[gem5-users] Re: How to see the sender state information of a response pkt

[bagchi95aritra--- via gem5-users]

Hi Rubel, Thanks for your response. 

I was looking for something different. I was trying to see the MSHR that sends 
a pkt downstream (and as a result added to the sender state stack of the pkt), 
and when the response to the pkt again returns at that MSHR, the top of the 
sender state stack is popped. At last I became able to see it. 

Thanks and regards,
Aritra
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[gem5-users] Question about multi-socket simulation for x86

[Chris Zhang via gem5-users]

Dear all,

I wonder is it possible to simulate a multi-socket machine for x86. I think
there is one such option with Arm named num-cluster
.
Does it exist an equivalent knob in x86?

Thanks!

Best,
Chris
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[gem5-users] Re: gem5 output directory cmd option problems

[Dimitrios Chasapis via gem5-users]

Hi Sam,

I am not sure how the python script works but I think what you want to 
do can be achieved by using the --outdir=DIR (or -d DIR) command line 
argument for the gem5 binary, not the script.  For example I think the 
correct way to do it in your example is this:


build/X86/gem5.opt --outdir=./test 
component_models/caches/cachesFIFO/cache_system.py 1


Best,

Dimitrios

On 4/9/2021 14:32, Sam Knapper via gem5-users wrote:

Hi all,

I am attempting to run a bunch of benchmarks in parallel and want to 
store each output in a separate directory so it is not overwritten. I 
have written my own system python script. When i run:


build/X86/gem5.opt component_models/caches/cachesFIFO/cache_system.py 
1 --outdir=./test


where ./test is an empty existing folder, the output is simply written 
back to the m5out dir, instead of this test dir. Is there something I 
need to enable in my python script to get the cmd line option to work, 
or am I just using it incorrectly?


Thanks for your help,

Sam

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http://bsc.es/disclaimer___
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[gem5-users] gem5 output directory cmd option problems

[Sam Knapper via gem5-users]

Hi all,

I am attempting to run a bunch of benchmarks in parallel and want to store
each output in a separate directory so it is not overwritten. I have
written my own system python script. When i run:

build/X86/gem5.opt component_models/caches/cachesFIFO/cache_system.py 1
--outdir=./test

where ./test is an empty existing folder, the output is simply written back
to the m5out dir, instead of this test dir. Is there something I need to
enable in my python script to get the cmd line option to work, or am I just
using it incorrectly?

Thanks for your help,

Sam
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[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

[Giacomo Travaglini via gem5-users]

Hi Wenqi,

I have found the problem; in order to fix it you should recompile the 
bootloaders from system/arm/bootloader/arm64 and replace all of them with the 
ones in M5_PATH/binaries
That solves the problem on my side.

I am gonna update the guest binaries tarball in gem5.org (I was going to do 
that anyway after the 21.0 release)

Kind Regards

Giacomo


> -Original Message-
> From: Giacomo Travaglini
> Sent: 07 April 2021 09:13
> To: Wenqi Yin ; gem5 users mailing list  us...@gem5.org>
> Subject: RE: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU
>
> Thanks Wenqi,
>
> I was about to suggest the same; please feel free to open a JIRA ticket at:
>
> https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/
>
> Kind Regards
>
> Giacomo
>
> > -Original Message-
> > From: Wenqi Yin 
> > Sent: 07 April 2021 06:40
> > To: gem5 users mailing list 
> > Cc: Giacomo Travaglini 
> > Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM
> > CPU
> >
> > Hi All,
> >
> > The problem turns out to be with the recent release v21.0. I rolled
> > back to v20.2, it can boot 8+ KVM cpu after applying all the changes
> discusses before.
> >
> > Shall I report this issue anywhere? If so is there any instructions to do 
> > so?
> > Thanks
> >
> > Best,
> > Wenqi
> >
> > > On Apr 6, 2021, at 11:54, wq...@utexas.edu wrote:
> > >
> > > Hi Giacomo,
> > >
> > > I pasted the perhaps most relevant dmesg output of guest kernel and
> > > the
> > disassembled dtb file snippet (In this case, I use fs_bigLittle.py and
> > boot 4
> > vCPU) . Also attached the full dts and dmesg output in case I left anything.
> > >
> > > [0.00] CPU features: GIC system register CPU interface present but
> > disab
> > > led by higher exception level
> > >
> > > [0.052000] smp: Bringing up secondary CPUs ...
> > > [2.004021] random: fast init done
> > > [2.132023] CPU1: failed to come online
> > > [2.132023] CPU1: failed in unknown state : 0x0
> > > [4.244045] CPU2: failed to come online
> > > [4.244045] CPU2: failed in unknown state : 0x0
> > > [6.356068] CPU3: failed to come online
> > > [6.356068] CPU3: failed in unknown state : 0x0
> > > [8.468091] CPU4: failed to come online
> > > [8.468091] CPU4: failed in unknown state : 0x0
> > > [8.468091] smp: Brought up 1 node, 1 CPU
> > >
> > >
> > > cpus {
> > > #address-cells = <0x1>;
> > > #size-cells = <0x0>;
> > >
> > > cpu@0 {
> > > device_type = "cpu";
> > > compatible = "gem5,arm-cpu";
> > > reg = <0x0>;
> > > enable-method = "spin-table";
> > > cpu-release-addr = <0x0 0x87f8>;
> > > clock-frequency = <0x773593ff>;
> > > phandle = <0xf>;
> > > };
> > >
> > > cpu@1 {
> > > device_type = "cpu";
> > > compatible = "gem5,arm-cpu";
> > > reg = <0x1>;
> > > enable-method = "spin-table";
> > > cpu-release-addr = <0x0 0x87f8>;
> > > clock-frequency = <0x773593ff>;
> > > phandle = <0x10>;
> > > };
> > >
> > > cpu@2 {
> > > device_type = "cpu";
> > > compatible = "gem5,arm-cpu";
> > > reg = <0x2>;
> > > enable-method = "spin-table";
> > > cpu-release-addr = <0x0 0x87f8>;
> > > clock-frequency = <0x773593ff>;
> > > phandle = <0x11>;
> > > };
> > >
> > > cpu@3 {
> > > device_type = "cpu";
> > > compatible = "gem5,arm-cpu";
> > > reg = <0x3>;
> > > enable-method = "spin-table";
> > > cpu-release-addr = <0x0 0x87f8>;
> > > clock-frequency = <0x773593ff>;
> > > phandle = <0x12>;
> > > };
> > >
> > > cpu@104 {
> > > device_type = "cpu";
> > > compatible = "gem5,arm-cpu";
> > > reg = <0x104>;
> > > enable-method = "spin-table";
> > > cpu-release-addr = <0x0 0x87f8>;
> > > clock-frequency = <0x3b9ac9ff>;
> > > phandle = <0x13>;
> > > };
> > > };
> > >
> > > best,
> > >
> > > Wenqi
> > >
> > > On 4/6/21 7:35 AM, Giacomo Travaglini wrote:
> > >> Hi Wenqi,
> > >>
> > >> Could you provide us with the booting log of the guest kernel?
> > >>
> > >> Kind Regards
> > >>
> > >> Giacomo
> > >>

[gem5-users] ARM FS per thread stats

[Pedro Becker via gem5-users]

Hi all, 

Does gem5 have a way to output stats per thread out-of-the-box? Stats.txt is 
fine, but as you know it reports stats per CPU.
FIY, I am running a multi-threaded application in arm64 FS mode.

I saw an option in fs.py:
--enable-context-switch-stats-dump
Enable stats dump at context switches and dump tasks
file (required for Streamline)

But it seems to be outdated:

  File "", line 1, in 
  File "build/ARM/python/m5/main.py", line 457, in main
exec(filecode, scope)
  File "configs/example/fs.py", line 339, in 
test_sys = build_test_system(np)
  File "configs/example/fs.py", line 108, in build_test_system
test_sys.enable_context_switch_stats_dump = True
  File "build/ARM/python/m5/SimObject.py", line 1362, in __setattr__
raise AttributeError("Class %s has no parameter %s" \
AttributeError: Class ArmSystem has no parameter 
enable_context_switch_stats_dump

Indeed, there is no such a param in the src/arch/arm/ArmSystem.py, so I guess 
this is dead code... 
Since this seemed to be used in the past I wonder if there are any other 
alternatives currently?

Thank you for any feedback!

Thank you.
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[gem5-users] Re: 回复：Re: can anyboby tell me how to generate the checpoints of spec2017?

[Miguel Antonio Avargues Gutiérrez via gem5-users]

Hello, you can run the following order:
/sbin/m5 checkpoint.

Greetings,
Miguel Antonio Avargues Guti??rrez.

El 08/04/2021 a las 17:19, ?? via gem5-users escribi??:

hi, Arthur,
?0?2 ?0?2 Thank you for replying to me. I think I used the wrong 
instructions for generating the checkpoints. There is no need to 
provide the context about the error. I just want some tutorials about 
how to generate the checkpoint, such as blogs, pdf.

?0?2 ?0?2 Thank you again.

--?0?2?0?2--
*??:* "gem5 users mailing list" ;
*:*?0?22021??4??8??(??) 11:04
*??:*?0?2"gem5-users";
*:*?0?2"Arthur Perais";
*:*?0?2[gem5-users] Re: can anyboby tell me how to generate the 
checpoints of spec2017?


Hi,

I think you will need to provide more context than this. We cannot 
help if we just know you encountered "a strange error".


Namely, if you are running FullSystem or SystemEmulation, what ISA, 
the command lines, etc...


Arthur

On 4/8/21 3:59 PM, ?? via gem5-users wrote:

hi, everyone,
?0?2 ?0?2 I m a beginner of gem5, now I want to generate the checkpoints of 
spec2017.?0?2 I follow the instructions from this 
page(https://www.gem5.org/documentation/general_docs/checkpoints), 
but some strange mistakes appeared.

?0?2 ?0?2so, can anyone give some advice or some tutorial? Thank you very much.


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