[gem5-users] test in Atomic is OK but in KVM is panic
Hi All:
I have tested my simple program, if I use AtomicSimple CPU, the result
is OK, but if I use X86KvmCpu, the result panic:
My simple program source code is:
#include
int main()
{
unsigned int a = 0;
unsigned long i;
for (i=0;i<1000;i++)
a++;
printf("charlie, charlie, charliel\n");
return 0;
}
root@ubuntu:/home/l00515693/whl/gem5# ./build/X86/gem5.opt
configs/example/se.py --cpu-type=AtomicSimpleCPU
--checkpoint-dir=/home/l00515693/whl/gem5/m5out/ --mem-size=2GB --num-cpus=1 -c
./test
warn: CheckedInt already exists in allParams. This may be caused by the Python
2.7 compatibility layer.
warn: Enum already exists in allParams. This may be caused by the Python 2.7
compatibility layer.
warn: ScopedEnum already exists in allParams. This may be caused by the Python
2.7 compatibility layer.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 version 20.0.0.3
gem5 compiled May 13 2021 00:01:52
gem5 started May 14 2021 13:04:12
gem5 executing on ubuntu, pid 9926
command line: ./build/X86/gem5.opt configs/example/se.py
--cpu-type=AtomicSimpleCPU --checkpoint-dir=/home/l00515693/whl/gem5/m5out/
--mem-size=2GB --num-cpus=1 -c ./test
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (2048 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
REAL SIMULATION
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
warn: ignoring syscall access(...)
charlie, charlie, charliel
root@ubuntu:/home/l00515693/whl/gem5#
root@ubuntu:/home/l00515693/whl/gem5# ./build/X86/gem5.opt
configs/example/se.py --cpu-type=X86KvmCPU
--checkpoint-dir=/home/l00515693/whl/gem5/m5out/ --mem-size=2GB --num-cpus=1 -c
./test
warn: CheckedInt already exists in allParams. This may be caused by the Python
2.7 compatibility layer.
warn: Enum already exists in allParams. This may be caused by the Python 2.7
compatibility layer.
warn: ScopedEnum already exists in allParams. This may be caused by the Python
2.7 compatibility layer.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 version 20.0.0.3
gem5 compiled May 13 2021 00:01:52
gem5 started May 14 2021 13:07:56
gem5 executing on ubuntu, pid 14352
command line: ./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU
--checkpoint-dir=/home/l00515693/whl/gem5/m5out/ --mem-size=2GB --num-cpus=1 -c
./test
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (2048 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
warn: CoherentXBar system.membus has no snooping ports attached!
REAL SIMULATION
info: KVM: Coalesced MMIO disabled by config.
warn: x86 cpuid family 0x: unimplemented function 2
warn: x86 cpuid family 0x: unimplemented function 3
warn: x86 cpuid family 0x: unimplemented function 4
warn: x86 cpuid family 0x: unimplemented function 5
warn: x86 cpuid family 0x: unimplemented function 6
info: Entering event queue @ 0. Starting simulation...
warn: kvm-x86: MSR (0x3a) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0xd90) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x48) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x12) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x11) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4b564d01) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4b564d00) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4000) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4001) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4020) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4021) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4100) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4101) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4102) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4103) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4104) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4105) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4003) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4002) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4010) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4080) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x40b0) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4073) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4b564d02) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4b564d03) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4b564d04) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x3b) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x6e
[gem5-users] Ruby strict fifo message buffer panic: FIFO ordering violated
Hi all, I was using the Ruby MESI_Three_Level protocol with strict ordered FIFO and hit a ordering violation. After some digging, I found that the cause of the issue. There are two events enqueue message to the same message buffer with different arrival delay, where the first executed one has higher delay and cause the violation. At tick 63032684, L1Cache_Controller executes forward_eviction_to_L0_else() and directly enqueues the message to the message queue of the L0Cache_Controller, but the arrival time is (curTick + l1_request_delay), where the l1_reqest_delay is the ticks for 2 cycles. So this will set the m_last_arrival_time to 63033256. At the same tick (63032684), L0Cache_Controller delay the head message due to blocking, and re-enqueue it to the end of the queue with a new arrival time, which is (curTick + cyclesToTicks(Cycles(1))), which is 63032970. So the second one's arrival time is less than the first one's arrival time, violating the strict fifo order. This is due to the arrival delay is accounted for after the message is enqueued to the message buffer. But two entities may directly enqueue messages to the same message buffer (even in the same cycle) with different arrival delays. Is the logic broken or there are some assumption for using strict fifo? Currently I disable the strict_fifo flag as a workaround. Any suggestions for fixing this issue? Please see the debug log below: The message buffer is system.ruby.l1_cntrl0.bufferFromL1, the L0Cache_Controller is system.ruby.l0_cntrl0, and the L1Cache_Controller is system.ruby.l1_cntrl0. - 63032398: system.ruby.l0_cntrl0.bufferFromL1: break here 63032398: system.ruby.l0_cntrl0.bufferFromL1: Enqueue arrival_time: 63032684, Message: [CoherenceMsg: addr = [0x11e580, line 0x11e580] Class = INV_ELSE pc = [0x0, line 0x0] AccessMode = User Sender = L1Cache-0 Dest = L0Cache-0 MessageSize = Control DataBlk = [ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 ] Dirty = 0 Prefetch = No ] 63032398: system.ruby.l0_cntrl0.mandatoryQueue: Peeking at head of queue. 63032398: system.ruby.l0_cntrl0.mandatoryQueue: Message: [RubyRequest: LineAddress = 0x3a2c0 PhysicalAddress = 0x3a2e0 Type = IFETCH ProgramCounter = 0x43a2e0 AccessMode = Supervisor Size = 16 Prefetch = No ] 63032398: system.ruby.l0_cntrl0.Dcache: No tag match for address: 0x3a2c0 63032398: system.ruby.l0_cntrl0.mandatoryQueue: Peeking at head of queue. 63032398: system.ruby.l0_cntrl0.mandatoryQueue: Message: [RubyRequest: LineAddress = 0x3a2c0 PhysicalAddress = 0x3a2e0 Type = IFETCH ProgramCounter = 0x43a2e0 AccessMode = Supervisor Size = 16 Prefetch = No ] 63032398: system.ruby.l0_cntrl0.mandatoryQueue: Popping 63032398: system.ruby.l0_cntrl0.Dcache: No tag match for address: 0x3a2c0 63032398: system.ruby.l1_cntrl0.requestFromL2: Enqueue arrival_time: 63032684, Message: [RequestMsg: addr = [0x26300, line 0x26300] Type = GETS pc = [0x5, line 0x0] AccessMode = User Requestor = L1Cache-1 Destination = [NetDest (17) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - 0 0 0 0 - - - - - - - - - - - - - ] MessageSize = Request_Control DataBlk = [ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 ] Len = 0 Dirty = 0 Prefetch = No ] 63032684: system.ruby.l1_cntrl10.responseFromL2: Enqueue arrival_time: 63032970, Message: [ResponseMsg: addr = [0x3a400, line 0x3a400] Type = DATA Sender = L2Cache-0 Destination = [NetDest (17) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - 0 0 0 0 - - - - - - - - - - - - - ] DataBlk = [ 0xb9 0x1 0x0 0x0 0x0 0x89 0xd0 0xf0 0x41 0xf 0xb1 0x8 0xf 0x84 0xbc 0xfe 0xff 0xff 0x4c 0x89 0xc7 0xe8 0x16 0xbf 0xfe 0xff 0xe9 0xaf 0xfe 0xff 0xff 0x90 0x87 0x7 0x83 0xf8 0x1 0x7e 0x8e 0x45 0x31 0xd2 0xba 0x1 0x0 0x0 0x0 0xbe 0x81 0x0 0x0 0x0 0xb8 0xca 0x0 0x0 0x0 0xf 0x5 0xe9 0x75 0xff 0xff 0xff ] Dirty = 0 AckCount = 0 MessageSize = Response_Data ] 63032684: system.ruby.l1_cntrl0.requestFromL2: Peeking at head of queue. 63032684: system.ruby.l1_cntrl0.requestFromL2: Message: [RequestMsg: addr = [0x26300, line 0x26300] Type = GETS pc = [0x5, line 0x0] AccessMode = User Requestor = L1Cache-1 Destination = [NetDest (17) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - 0 0 0 0 - - - - - - - - - - - - - ] MessageSize = Request_Control DataBlk = [ 0x0 0x0 0x0 0x0 0x0 0
[gem5-users] Regarding Cache Clusivity
Hi gem5 community, TL;DR: 1. In "classic" memory, the current 2 options, mostly_incl and mostly_excl, seem to apply only to cache fill but NOT eviction. As a result, blocks evicted from L2 may be still present in L1. Is my understanding correct? 2. What would be a reasonable way to enforce strict inclusivity and exclusivity? -- Details: This link may provide some background: https://m5-dev.m5sim.narkive.com/qRrXUtt7/gem5-dev-review-request-3156-mem-add-cache-clusivity-to-steer-behaviour-on-fill 1. In the case of a replacement eviction, BaseCache::allocateBlock() finds a victim and then calls BaseCache::handleEvictions() >> BaseCache::evictBlock() >> Cache::evictBlock(). As a result, a packet is pushed into writebacks list. doWritebacks() doesn't seem to bother upstream caches that hold the same block. 2. To implement strict inclusivity, the most obvious way to me is letting doWritebacks() send an invalidation packet through cpuSidePort. But I don't know how to stitch these things together without breaking other stuff. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Tracing Instructions in gem5 (re: Adding a New Instruction)
Hi Everyone, I am fairly new to gem5, so I apologize if this has already been addressed, but I haven't been able to find a solution yet. I am trying to add a new type of store instruction to gem5 similar to the STG instruction from ARM's MTE instructions. I was wondering if there was a debug flag or an approach using GDB to determine what files are used when processing an instruction in gem5. I have tried all of the debug flags that I thought might be relevant, and tried to debug it using GDB, but none of the flags seem to output the files/functions/classes that an instruction uses and GDB only seems to output the files/functions related to the build environment and C libraries and it seems to debug the src/sim/main.cc file rather than the instructions in the executable that I am trying to run, so I am not sure if I am doing something wrong. I've also tried using the python debugger (PDB), but it seems to be doing something similar to GDB, as I can't seem to get it to show the files that are accessed when processing an instruction. I know that I can create my own debug flags, but with so many files/functions available, I am worried I will have to have a DPRINTF() in every file/function/class, and I'm not entirely sure if I can use DPRINTF() statements in some of the file extension types. I did find an example online adding an instruction in ARM in a slightly similar way (https://www.cl.cam.ac.uk/~rmk35/gem5-instruction.html), but it is causing a panic error right now when I run it, and it has a slightly different setup then the regular instructions that already exist in gem5, so I want to make sure I am understanding how instructions are processed in gem5, especially since I am assuming I will need to change more things to get the new store instruction to work properly. I am aware of some of the general files that need to be edited, such as: src/arch/arm/isa/formats/aarch64.isa src/arch/arm/isa/templates/mem64.isa src/arch/arm/isa/insts/str64.isa But I would like to be able to see all of these files/functions/classes as they are used/touched as an instruction is processed through gem5. For instance, seeing what things are accessed when a STR instruction that already is implemented in gem5 is being processed. Any help or advice would be greatly appreciated. Thank you for your time! Respectfully, Jason Z. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Early append of python link-flags shadows LD_LIBRARY_PATH and LDFLAGS_EXTRA for Linux build
When building on RHEL7, in the case where python has not been suppressed via '--without-python' (i.e. USE_PYTHON is true), the SConstruct file uses 'python[3]-config --libs --embed' or 'python[3]-config --ldflags' to get a list of tokens. It then selects anything not starting with '-l' to append to LINKFLAGS. In my case, these flags include '-L/usr/lib64'. This step is early in the process of building LINKFLAGS. Anything later extracted from the environment, or specified via LDFLAGS_EXTRA, is appended to LINKFLAGS after this. The effect is that I can't override any library that is found at link-time in /usr/lib64. For example, I've spent some time trying to figure out why my custom-built libprotobuf was not resolving undefined symbols in the gem5 link. Suppressing the addition of this '-L/usr/lib64' to the link-flags allows me to get past that problem, since my own version of the library is now used, but this is probably not the right fix, in general. Thanks, Jeff ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Boot FS with kvm and multiple cores
Update. I was reading a related discussion in the archive (https://www.mail-archive.com/gem5-users@gem5.org/msg19217.htm) where the OP reported they could successfully run kvm up to 8 cores with the configs/example/arm/fs_bigLITTLE.py script. So I tried running gem5 with his parameters and the arm/fs_bigLITTLE.py. The following boots correctly: ./build/ARM/gem5.opt configs/example/arm/fs_bigLITTLE.py --kernel $M5_PATH/binaries/vmlinux.arm64 --machine-type VExpress_GEM5 --disk /scratch/pedro/ubuntu-18.04-arm64-docker.img --cpu-type kvm --big-cpus 4 But the following do not (boot get stuck right in the beginning): ./build/ARM/gem5.opt configs/example/fs.py --kernel $M5_PATH/binaries/vmlinux.arm64 --machine-type VExpress_GEM5 --disk-image /scratch/pedro/ubuntu-18.04-arm64-docker.img --cpu-type ArmV8KvmCPU --num-cpus 4 So I think there might be something I can adapt from fs_bigLITTLE to run with fs.py. Any hints on this are welcome, but I still need to review the differences, so it might be simple to fix. The main problem I still have is fs_bigLITTLE.py with --big-cpus 8 (I want to have an 8-core setup) causes panic: info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x8008 info: Loading DTB file: m5out/system.dtb at address 0x8800 info: KVM: Coalesced MMIO disabled by config. info: KVM: Coalesced MMIO disabled by config. info: KVM: Coalesced MMIO disabled by config. info: KVM: Coalesced MMIO disabled by config. info: KVM: Coalesced MMIO disabled by config. info: KVM: Coalesced MMIO disabled by config. info: KVM: Coalesced MMIO disabled by config. info: KVM: Coalesced MMIO disabled by config. panic: KVM: Failed to create virtual CPU Memory Usage: 2619720 KBytes Program aborted at tick 0 --- BEGIN LIBC BACKTRACE --- ./build/ARM/gem5.opt(_Z15print_backtracev+0x40)[0x5576c8e090] ./build/ARM/gem5.opt(_Z12abortHandleri+0x5c)[0x55770cbdb4] linux-vdso.so.1(__kernel_rt_sigreturn+0x0)[0x7f9b01e6c0] /lib/aarch64-linux-gnu/libc.so.6(raise+0xb0)[0x7f9abe94f8] --- END LIBC BACKTRACE --- Aborted (core dumped) I saw some discussion on gem5 supporting gicv2 but not gicv3, but from what I read even the former should support up to 8 cores. So I'm not sure this is the problem here. Any suggestions? Thanks, Pedro. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] FAST-FORWARD Option in Simulation
Hello, Please help me to know how to use the Fast Forward Option so that I can get statistics for simulation excluding the initial Cache misses. I had specified --fast-forward=1000 but in the stats file everything is 0. I am using Ruby system with garnet network. Following is the message on terminal: Switched CPUS @ tick 509500 switching cpus warn: ClockedObject: Already in the requested power state, request ignored REAL SIMULATION info: Entering event queue @ 509500. Starting simulation... Exiting @ tick 509500 because a thread reached the max instruction count I have heard that in Ruby it can be done with checkpoints instead of fast-forward. If that is so, please tell me how to accomplish that. Thank you, Vedika. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Boot FS with kvm and multiple cores
Hi all, I'm trying to boot Linux (from https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries) with multiple cores and KVM. The target ISA is aarch64, so I am running gem5 on an aarch64 host machine, with KVM support. I'm trying with the latest stable gem5 version (v21.0.0.0) and the latest images from guest binaries. I'm using the fs.py script, and the boot works if I run it with only one CPU: ``` ./build/ARM/gem5.opt configs/example/fs.py --kernel $M5_PATH/binaries/vmlinux.arm64 --disk-image /scratch/pedro/ubuntu-18.04-arm64-docker.img --cpu-type ArmV8KvmCPU --mem-size 8GB --script configs/boot/my_test_script.rcS --num-cpus 1 ``` But if I run with `--num-cpus 2` (or 4 or 8), the terminal gets stuck at: ``` warn: Returning zero for read from miscreg pmevtyper2_el0 warn: Returning zero for read from miscreg pmevtyper3_el0 warn: Returning zero for read from miscreg pmevtyper4_el0 warn: Returning zero for read from miscreg pmevtyper5_el0 warn: Returning zero for read from miscreg pmccfiltr_el0 ``` With only one CPU the terminal rapidly progresses after that part: ``` warn: Returning zero for read from miscreg pmevtyper1_el0 warn: Returning zero for read from miscreg pmevtyper2_el0 warn: Returning zero for read from miscreg pmevtyper3_el0 warn: Returning zero for read from miscreg pmevtyper4_el0 warn: Returning zero for read from miscreg pmevtyper5_el0 warn: Returning zero for read from miscreg pmccfiltr_el0 warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist warn: EnergyCtrl: Disabled handler, ignoring read from reg 0 ``` And I can attach the terminal and see things are ok. So questions: Is KVM with multiple cores supported by gem5? I thought so by looking here http://www.gem5.org/documentation/benchmark_status/gem5-20 If it is, should I give any additional flags or perform additional steps in order to run KVM with multiple cores? Thank you in advance for any suggestions, Pedro. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Gem5 in FS mode
Hi, If you want to run a binary that is inside the Linux image, then fs.py has a --script flag, which you can use. It allows you to pass a .rcS script to be read inside FS simulation through the /sbin/m5_readfile, which you can redirect to a local file (inside the simulation) and then execute. The script can then call your application. The gem5/configs/boot/ folder contains some .rcS scripts if you want to check out. The /init.gem5 scripts inside the guest binaries (https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries) - which is executed in the end of the boot - exemplify how these scripts can be read and used. Your image seems to be a different one so you might have to adapt to your case. Also, I asked a similar question not long ago, which might help you: https://www.mail-archive.com/gem5-users@gem5.org/msg19180.html Cheers, Pedro. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Gem5 in FS mode
Hello, I want to run my own binary file in FS mode of gem5 . I am using following command : "time build/ALPHA_MESI_Two_Level/gem5.opt configs/example/fs.py --cpu-type=TimingSimpleCPU --kernel=/home/coep/gem5/alpha_fsi/binaries/vmlinux_2.6.27-gcc_4.3.4 --disk-image=/home/coep/gem5/alpha_fsi/disks/linux-parsec-2-1-m5-with-test-inputs.img --ruby --l2cache -n16" Which command I should add to run my binary file. or there is any steps that i have to perform to run binary file of my code in FS mode of gem5 ?? Thank you in advance. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
