[gem5-users] Re: Assistance required: Stats not generated for TLM examples
Hi PaiJ,
Is the stats.txt file in m5out folder is empty? If yes, I think the root cause
is that gem5-tlm is using cxx_manager class to register each objects while the
registering of stat is missing.
My solution is adding a new method at CxxConfigManager::instantiate(bool
build_all){} . This method will iterate through all the simObjects and add
their stats into gem5::statistics::statsList().
Due to work reasons, I can't give you the code directly. Hope this can give you
a hint.
Thanks + Regards,
Ziyang
From: Ananth.PaiJ--- via gem5-users
Sent: Tuesday, January 9, 2024 11:53 AM
To: gem5-users@gem5.org
Cc: ananth.p...@infineon.com
Subject: [gem5-users] Assistance required: Stats not generated for TLM examples
Hello all,
I have been working with gem5 for a while now. I'm trying to generate
statistics for the TLM example given in the
util/systemc/systemc_within_gem5/systemc_gem5_tlm example.
Since there were no in-built stats available for the sc_tlm_target.{cc,hh}, I
tried to create few of my own using the mechanism given in the documentation.
I'll add my code snippets below.
#include<>
struct TargetParams: public SimObjectParams{
};
class Target: public sc_module, public gem5::SimObject
{
public:
..
struct StatGroup : public gem5::statistics::Group {
gem5::statistics::Scalar testingVariable1;
gem5::statistics::Scalar testingVariable2;
gem5::statistics::Scalar testingVariable3;
StatGroup(gem5::statistics::Group *parent);
}stats;
public:
PARAMS(Target);
SC_HAS_PROCESS(Target);
Target(sc_module_name name, const Params ) :
sc_module(name),
SimObject(p),
tSocket("tSocket"),
wrapper(tSocket, std::string(name) + ".tlm", InvalidPortID),
stats(this)
{
.
}
.
};
Target::StatGroup::StatGroup(gem5::statistics::Group *parent)
: gem5::statistics::Group(parent),
ADD_STAT(testingVariable1, gem5::statistics::units::Count::get(),
"Variable1 for testing"),
ADD_STAT(testingVariable2, gem5::statistics::units::Count::get(),
"Variable2 for testing"),
ADD_STAT(testingVariable3, gem5::statistics::units::Count::get(),
"Variable3 for testing")
{
}
My current gem5 version is gem5v23.1. I'm working on WSL. Please feel ask any
more questions if needed.
Thank you and hoping to listen from you soon.
Best Regards,
Ananth Pai J
Infineon Technologies IN
DES PTS TI EA SME
Phone: +91 7349045724
ananth.p...@infineon.com
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[gem5-users] Assistance required: Stats not generated for TLM examples
Hello all,
I have been working with gem5 for a while now. I'm trying to generate
statistics for the TLM example given in the
util/systemc/systemc_within_gem5/systemc_gem5_tlm example.
Since there were no in-built stats available for the sc_tlm_target.{cc,hh}, I
tried to create few of my own using the mechanism given in the documentation.
I'll add my code snippets below.
#include<>
struct TargetParams: public SimObjectParams{
};
class Target: public sc_module, public gem5::SimObject
{
public:
..
struct StatGroup : public gem5::statistics::Group {
gem5::statistics::Scalar testingVariable1;
gem5::statistics::Scalar testingVariable2;
gem5::statistics::Scalar testingVariable3;
StatGroup(gem5::statistics::Group *parent);
}stats;
public:
PARAMS(Target);
SC_HAS_PROCESS(Target);
Target(sc_module_name name, const Params ) :
sc_module(name),
SimObject(p),
tSocket("tSocket"),
wrapper(tSocket, std::string(name) + ".tlm", InvalidPortID),
stats(this)
{
.
}
.
};
Target::StatGroup::StatGroup(gem5::statistics::Group *parent)
: gem5::statistics::Group(parent),
ADD_STAT(testingVariable1, gem5::statistics::units::Count::get(),
"Variable1 for testing"),
ADD_STAT(testingVariable2, gem5::statistics::units::Count::get(),
"Variable2 for testing"),
ADD_STAT(testingVariable3, gem5::statistics::units::Count::get(),
"Variable3 for testing")
{
}
My current gem5 version is gem5v23.1. I'm working on WSL. Please feel ask any
more questions if needed.
Thank you and hoping to listen from you soon.
Best Regards,
Ananth Pai J
Infineon Technologies IN
DES PTS TI EA SME
Phone: +91 7349045724
ananth.p...@infineon.com
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[gem5-users] Full System emulation using bare metal option
Hi everyone, I would need to run a simulation of gem5 in Full System emulation
with RISCV architecture with a simple C program. I therefore tried to use the
--bare-metal option.
So, I tried to run the following command:
`./gem5/build/RISCV/gem5.opt ./gem5/configs/example/riscv/fs_linux.py
--kernel=test —bare-metal`
where "test" is a compiled program written in C:
> #include
>
> int main(void){
>
>unsigned int r = 1337;
>
>printf("Hello World! %d\\n", r);
>
>while (1) { }
>
> }
and compiled with the following command: `riscv64-unknown-linux-gnu-gcc
--static test.c -o test`
but gem5 returns me the following error:
> gem5 Simulator System. https://www.gem5.org
>
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version 23.0.1.0
>
> gem5 compiled Dec 15 2023 12:35:45
>
> gem5 started Jan 8 2024 12:55:50
>
> gem5 executing on 46f410d0d38b, pid 1704898
>
> command line: ./gem5/build/RISCV/gem5.opt
> ./gem5/configs/example/riscv/fs_linux.py --kernel=test —bare-metal
>
> warn: The \`get_runtime_isa\` function is deprecated. Please migrate away
> from using this function.
>
> warn: The \`get_runtime_isa\` function is deprecated. Please migrate away
> from using this function.
>
> Global frequency set at 1 ticks per second
>
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
>
> src/mem/dram_interface.cc:690: warn: DRAM device capacity (8192 Mbytes) does
> not match the address range assigned (512 Mbytes)
>
> src/base/statistics.hh:279: warn: One of the stats is a legacy stat. Legacy
> stat is a stat that does not belong to any statistics::Group. Legacy stat is
> deprecated.
>
> 0: system.platform.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
>
> system.platform.terminal: Listening for connections on port 3456
>
> system.remote_gdb: Listening for connections on port 7000
>
> \*\*\*\* REAL SIMULATION \*\*\*\*
>
> src/sim/simulate.cc:194: info: Entering event queue @ 0. Starting
> simulation...
>
> src/cpu/simple/atomic.cc:753: panic: panic condition pkt.isError() occurred:
> Instruction fetch (\[0x10420:0x10424\]) failed: BadAddressError
> \[10420:10423\] IF
>
> Memory Usage: 626284 KBytes
>
> Program aborted at tick 0
>
> \--- BEGIN LIBC BACKTRACE ---
>
> gem5.opt(+0x63c370)\[0x56510fbd8370\]
>
> gem5.opt(+0x66b7ac)\[0x56510fc077ac\]
>
> /lib/x86_64-linux-gnu/libc.so.6(+0x42520)\[0x7f32bd310520\]
>
> /lib/x86_64-linux-gnu/libc.so.6(pthread_kill+0x12c)\[0x7f32bd3649fc\]
>
> /lib/x86_64-linux-gnu/libc.so.6(raise+0x16)\[0x7f32bd310476\]
>
> /lib/x86_64-linux-gnu/libc.so.6(abort+0xd3)\[0x7f32bd2f67f3\]
>
> gem5.opt(+0x654825)\[0x56510fbf0825\]
>
> gem5.opt(+0xb92873)\[0x56511012e873\]
>
> gem5.opt(+0xb91920)\[0x56511012d920\]
>
> gem5.opt(+0x657612)\[0x56510fbf3612\]
>
> gem5.opt(+0x6953b8)\[0x56510fc313b8\]
>
> gem5.opt(+0x6959ab)\[0x56510fc319ab\]
>
> gem5.opt(+0x132e8f0)\[0x5651108ca8f0\]
>
> gem5.opt(+0x5d0b74)\[0x56510fb6cb74\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x128023)\[0x7f32bde0f023\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyObject_Call+0x5c)\[0x7f32bddc8fec\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x4b16)\[0x7f32bdd5d776\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c23af)\[0x7f32bdea93af\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d68)\[0x7f32bdd629c8\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c23af)\[0x7f32bdea93af\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x69de)\[0x7f32bdd5f63e\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c23af)\[0x7f32bdea93af\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d68)\[0x7f32bdd629c8\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c23af)\[0x7f32bdea93af\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(PyEval_EvalCode+0xbe)\[0x7f32bdea43de\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1bd96d)\[0x7f32bdea496d\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1287b3)\[0x7f32bde0f7b3\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x69de)\[0x7f32bdd5f63e\]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c23af)\[0x7f32bdea93af\]
>
> gem5.opt(+0x66e2f7)\[0x56510fc0a2f7\]
>
> gem5.opt(+0x3cff1b)\[0x56510f96bf1b\]
>
> /lib/x86_64-linux-gnu/libc.so.6(+0x29d90)\[0x7f32bd2f7d90\]
>
> \--- END LIBC BACKTRACE ---
>
> For more info on how to address this issue, please visit
> https://www.gem5.org/documentation/general_docs/common-errors/
>
> Aborted (core dumped)
How can I fix it?
Is it correct to use the bare-metal option? Or can I do it some other way?
Does the C program need any dependencies?
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[gem5-users] Re: Transient execution during Page Fault - X86 O3 FS simulation
I analyzed a few debug log outputs. The control flow varies here https://github.com/gem5/gem5/blob/stable/src/cpu/o3/commit.cc#L1172, when the instruction triggers the page fault in the TLB. Whether or not I remove this check for a fault in the commit step for my address, the instruction remains unchanged if the PageFault is triggered earlier. Without PageFault: "MOVSX_B_R_M : ld t1b, DS:[rax] : MemRead : D=0x00401753 A=0x7f5bd1b11000" With PageFault: "MOVSX_B_R_M : ld t1b, DS:[rax] : MemRead : A=0x7f5bd1b11000" Is my assumption correct, that a PageFault leads to an earlier "ignoring" of the instruction and therefore, the value isn't even computed, rather than computed upfront and "deleted" after? Only without PageFault, the next parts of the instruction is also executed: "MOVSEX_B_R_M : sexti rcx, t1, 0x7 : IntAlu : D=0053" Kind regards Robin Gesendet: Freitag, 29. Dezember 2023 um 19:32 Uhr Von: "reverent.green--- via gem5-users" An: gem5-users@gem5.org Cc: reverent.gr...@web.de Betreff: [gem5-users] Transient execution during Page Fault - X86 O3 FS simulation Hello everyone, I am currently looking into transient execution vulnerabilities using the gem5 simulator. I successfully tried out the spectre example and want to create something similar for meltdown. For these experiments, I am using the O3 CPU model. - The first step was to change the simulation from SE to FS in order to have the kernel space memory mapped. - I'm using a modified meltdown PoC, which creates two mappings to the same shared memory and clears the User/Supervisor Bit for one of them. (https://github.com/IAIK/transientfail/tree/master/pocs/meltdown/US) - After accessing the mapping, it returns the Page Fault after checking the user bit of the PTE (https://github.com/gem5/gem5/blob/stable/src/arch/x86/tlb.cc#L476) Now my question: When I remove this user/supervisor check in gem5 specifically for my address, the PoC leaks the "secret" value via Flush+Reload without a problem, because it can be accessed and therefore should be in the cache. But when the Page Fault is created, the value is not leaked. I try to follow the execution chain for the specific PC and address shown for the triggered page fault for multiple weeks, but up until now failed to identify the exact problems here. Can someone enlighten me, how gem5 handles an instruction after this specific point? In my understanding, the transient execution should still be visible after the security check. Where is the exact point the instruction results are "removed", s.t. they aren't available in the cache anymore and in which step of the out-of-order pipeline does the magic happen? If you have further questions, I try to answer them as detailed as possible. Any tips would be really appreciated, thank you in advance. Kind regards Robin ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
