Re: [gem5-users] Integrated DRAMPower model
Hi Andreas, > a. there is a parameter, device_size, for the DDR3_1600_x64 config in > DRAMCtrl.py it is 512 Mbyte, or 4 Gbit. > Ahh ok it has been recently added. I was on commit 10433 where this parameter doesn't exist. So gem5 by default simulates 8GB DDR3 capacity? This is calculated as: device_size * number_of_devices * number_of_ranks * number_of_channels 512MB * 8 * 2 * 1 = 8GB Is this correct? Thanks for the help. Best Regards, Hassan > > Andreas > > From: Ahmad Hassan > Date: Thursday, 27 November 2014 08:59 > To: Andreas Hansson > Cc: Amin Farmahini , gem5 users mailing list < > gem5-users@gem5.org> > > Subject: Re: [gem5-users] Integrated DRAMPower model > > Hi Andreas, > > Thanks for the pointers. From the existing DDR3_1600_x64 configuration > parameters below, how do I calculate the a) size of 1 DD3 device b) Size of > 1 rank c) Size of full DDR3 (which is 4GB) > > device_bus_width = 8 > devices_per_rank = 8 > ranks_per_channel = 2 > banks_per_rank = 8 > > I am interested in knowing how a), b) and c) are calculated. Please can > you give describe this. Thanks > > Best Regards, Hassan > > > On 27 November 2014 at 08:36, Andreas Hansson > wrote: > >> Hi all, >> >> I think a quick fix is to expose the number of ranks on the command >> line. That give at least a level of flexibility, assuming everyone is happy >> with me adding that parameter. >> >> By then tuning the number of channels and ranks, you can at least >> choose how many of the existing DDR3 devices you instantiate. As Amin says, >> if you want anything less than 512 MB you would need to find a new data >> sheet though. The only DRAM configs that get in that range are the LPDDR2 >> and LPDDR3 ones as they use x32 devices. >> >> Andreas >> >> From: Amin Farmahini >> Date: Thursday, November 27, 2014 at 12:23 AM >> To: Ahmad Hassan , gem5 users mailing list < >> gem5-users@gem5.org> >> Cc: Andreas Hansson >> >> Subject: Re: [gem5-users] Integrated DRAMPower model >> >> To correctly get energy numbers you need to set the right set of >> current values (e.g. IDD2N) for your specific device. For example, 1Gb DDR3 >> devices have different current values from 8Gb DDR3 devices. You can find >> those values in manufacturers dustsheets. >> >> Each rank has a number of devices (devices_per_rank) which is usually 4 >> or 8 excluding ECC. For example, if you have 4 DDR3 devices in a rank each >> with a 1Gb capacity, your rank size is 512MB. >> >> Thanks, >> Amin >> >> >> On Wed, Nov 26, 2014 at 5:35 PM, Ahmad Hassan via gem5-users < >> gem5-users@gem5.org> wrote: >> >>> Hi Andreas, >>> >>> Thanks. I have seen DDR3 parameters device_bus_width, devices_per_rank, >>> ranks_per_channel and banks_per_rank defined in DRAMCtrl.py. I don't know >>> how they can add up to 4GB main memory as the size of rank is unknown in >>> the whole configuration. How can change parameters to simulate 128MB DDR3 >>> memory with 1 RANK? >>> >>> Thanks. >>> >>> >>> >>> On 26 November 2014 at 20:48, Andreas Hansson >>> wrote: >>> >>>> Hi Ahmad, >>>> >>>> The model captures the background energy. There is just no connection >>>> between “--mem-size” and the actual DRAM configuration (channel count, rank >>>> count, die size etc). There is currently a warning printed when there is a >>>> mismatch between the two, but to avoid having every user know about the >>>> details of the DRAM, we choose to not couple the two. >>>> >>>> If you want to change the actual DRAM capacity modelled you have to >>>> adapt the number of channels, ranks, die configuration etc, to match the >>>> density you are looking for. >>>> >>>> I hope that addresses your concern. >>>> >>>> Andreas >>>> >>>> From: Ahmad Hassan >>>> Date: Wednesday, 26 November 2014 18:58 >>>> >>>> To: Andreas Hansson >>>> Cc: gem5 users mailing list >>>> Subject: Re: [gem5-users] Integrated DRAMPower model >>>> >>>> Hi Andreas, >>>> >>>> I noticed one issue with the existing energy model. The current model >>>> is not modeling the background energy of DDR3 DRAM. If I run a benchmark >>>> with 128MB DRAM vs 16GB DRAM, the total energy stays the same. I want t
Re: [gem5-users] Integrated DRAMPower model
Hi Andreas, Thanks for the pointers. From the existing DDR3_1600_x64 configuration parameters below, how do I calculate the a) size of 1 DD3 device b) Size of 1 rank c) Size of full DDR3 (which is 4GB) device_bus_width = 8 devices_per_rank = 8 ranks_per_channel = 2 banks_per_rank = 8 I am interested in knowing how a), b) and c) are calculated. Please can you give describe this. Thanks Best Regards, Hassan On 27 November 2014 at 08:36, Andreas Hansson wrote: > Hi all, > > I think a quick fix is to expose the number of ranks on the command > line. That give at least a level of flexibility, assuming everyone is happy > with me adding that parameter. > > By then tuning the number of channels and ranks, you can at least choose > how many of the existing DDR3 devices you instantiate. As Amin says, if you > want anything less than 512 MB you would need to find a new data sheet > though. The only DRAM configs that get in that range are the LPDDR2 and > LPDDR3 ones as they use x32 devices. > > Andreas > > From: Amin Farmahini > Date: Thursday, November 27, 2014 at 12:23 AM > To: Ahmad Hassan , gem5 users mailing list < > gem5-users@gem5.org> > Cc: Andreas Hansson > > Subject: Re: [gem5-users] Integrated DRAMPower model > > To correctly get energy numbers you need to set the right set of > current values (e.g. IDD2N) for your specific device. For example, 1Gb DDR3 > devices have different current values from 8Gb DDR3 devices. You can find > those values in manufacturers dustsheets. > > Each rank has a number of devices (devices_per_rank) which is usually 4 > or 8 excluding ECC. For example, if you have 4 DDR3 devices in a rank each > with a 1Gb capacity, your rank size is 512MB. > > Thanks, > Amin > > > On Wed, Nov 26, 2014 at 5:35 PM, Ahmad Hassan via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi Andreas, >> >> Thanks. I have seen DDR3 parameters device_bus_width, devices_per_rank, >> ranks_per_channel and banks_per_rank defined in DRAMCtrl.py. I don't know >> how they can add up to 4GB main memory as the size of rank is unknown in >> the whole configuration. How can change parameters to simulate 128MB DDR3 >> memory with 1 RANK? >> >> Thanks. >> >> >> >> On 26 November 2014 at 20:48, Andreas Hansson >> wrote: >> >>> Hi Ahmad, >>> >>> The model captures the background energy. There is just no connection >>> between “--mem-size” and the actual DRAM configuration (channel count, rank >>> count, die size etc). There is currently a warning printed when there is a >>> mismatch between the two, but to avoid having every user know about the >>> details of the DRAM, we choose to not couple the two. >>> >>> If you want to change the actual DRAM capacity modelled you have to >>> adapt the number of channels, ranks, die configuration etc, to match the >>> density you are looking for. >>> >>> I hope that addresses your concern. >>> >>> Andreas >>> >>> From: Ahmad Hassan >>> Date: Wednesday, 26 November 2014 18:58 >>> >>> To: Andreas Hansson >>> Cc: gem5 users mailing list >>> Subject: Re: [gem5-users] Integrated DRAMPower model >>> >>> Hi Andreas, >>> >>> I noticed one issue with the existing energy model. The current model >>> is not modeling the background energy of DDR3 DRAM. If I run a benchmark >>> with 128MB DRAM vs 16GB DRAM, the total energy stays the same. I want to >>> count background energy of DRAM when sitting idle, Please can you tell me, >>> what changes shall I make to the existing code in order to count the >>> background energy of DRAM precisely? The continuous background energy of >>> DRAM is proportional to the size of simulated DRAM and I need to model this. >>> >>> Thanks. >>> >>> Regards, >>> >>> >>> >>> On 10 October 2014 at 15:34, Ahmad Hassan >>> wrote: >>> >>>> >>>> Indeed. That works without any warnings/errors: >>>> >>>> scons --no-lto -j10 build/X86/gem5.fast >>>> >>>> Regards, >>>> >>>> >>>> On 10 October 2014 13:11, Andreas Hansson >>>> wrote: >>>> >>>>> Hi Ahmad, >>>>> >>>>> I suspect gcc 4.6 has issues with LTO. I suspect opt works fine, and >>>>> if you want fast, then “--no-lto” should work. >>>>> >>>>> I have a 12.04.03 machine with
Re: [gem5-users] Integrated DRAMPower model
Hi Andreas, Thanks. I have seen DDR3 parameters device_bus_width, devices_per_rank, ranks_per_channel and banks_per_rank defined in DRAMCtrl.py. I don't know how they can add up to 4GB main memory as the size of rank is unknown in the whole configuration. How can change parameters to simulate 128MB DDR3 memory with 1 RANK? Thanks. On 26 November 2014 at 20:48, Andreas Hansson wrote: > Hi Ahmad, > > The model captures the background energy. There is just no connection > between “--mem-size” and the actual DRAM configuration (channel count, rank > count, die size etc). There is currently a warning printed when there is a > mismatch between the two, but to avoid having every user know about the > details of the DRAM, we choose to not couple the two. > > If you want to change the actual DRAM capacity modelled you have to > adapt the number of channels, ranks, die configuration etc, to match the > density you are looking for. > > I hope that addresses your concern. > > Andreas > > From: Ahmad Hassan > Date: Wednesday, 26 November 2014 18:58 > > To: Andreas Hansson > Cc: gem5 users mailing list > Subject: Re: [gem5-users] Integrated DRAMPower model > > Hi Andreas, > > I noticed one issue with the existing energy model. The current model is > not modeling the background energy of DDR3 DRAM. If I run a benchmark with > 128MB DRAM vs 16GB DRAM, the total energy stays the same. I want to count > background energy of DRAM when sitting idle, Please can you tell me, what > changes shall I make to the existing code in order to count the background > energy of DRAM precisely? The continuous background energy of DRAM is > proportional to the size of simulated DRAM and I need to model this. > > Thanks. > > Regards, > > > > On 10 October 2014 at 15:34, Ahmad Hassan wrote: > >> >> Indeed. That works without any warnings/errors: >> >> scons --no-lto -j10 build/X86/gem5.fast >> >> Regards, >> >> >> On 10 October 2014 13:11, Andreas Hansson >> wrote: >> >>> Hi Ahmad, >>> >>> I suspect gcc 4.6 has issues with LTO. I suspect opt works fine, and >>> if you want fast, then “--no-lto” should work. >>> >>> I have a 12.04.03 machine with stock gcc 4.6 and it does have some >>> link-time warnings for X86, but no errors. Odd… >>> >>> Andreas >>> >>> From: Ahmad Hassan >>> Date: Friday, 10 October 2014 10:51 >>> To: Andreas Hansson >>> Cc: gem5 users mailing list >>> >>> Subject: Re: [gem5-users] Integrated DRAMPower model >>> >>> Hi Andreas, >>> >>> My environment is: >>> Ubuntu precise (12.04.3 LTS) >>> gcc 4.6 >>> >>> To be precise, it is a linking error, not the compilation one. >>> >>> Regards, >>> >>> >>> On 10 October 2014 10:42, Andreas Hansson >>> wrote: >>> Hi Ahmad, That is odd. Could you elaborate on what environment you are building in? I’ve tested this on Ubuntu 12.04, RHE5/6 and OSX with clang 3.4/3.5, gcc 4.6 and 4.9 without any problems. Andreas From: Ahmad Hassan Date: Friday, 10 October 2014 09:51 To: Andreas Hansson , gem5 users mailing list Subject: Re: [gem5-users] Integrated DRAMPower model Thanks Andreas. I see compilation error on the trunk tip (changeset: 10433:821cbe4a183b) `std::basic_string, std::allocator > std::operator+, std::allocator >(char const*, std::basic_string, std::allocator > const&)' referenced in section `.text._Z10fromStringIiET_RKSsPFRSt8ios_baseS4_E[int fromString(std::basic_string, std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of build/drampower/libdrampower.a(Parameter.os): defined in discarded section `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of build/X86/mem/cache/base.fo (symbol from plugin) `std::basic_string, std::allocator > std::operator+, std::allocator >(char const*, std::basic_string, std::allocator > const&)' referenced in section `.text._Z10fromStringIjET_RKSsPFRSt8ios_baseS4_E[unsigned int fromString(std::basic_string, std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of build/drampower/libdrampower.a(Parameter.os): defined in discarded section `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of build/X86/mem/cache/base.fo (symbol from plugin) `std::basic_string, std::allocator > std::operator+, std::allocator >(char const*, std::basic_string, std::allocator > const&)' referenced in section `.text._Z10fromStringImET_RKSsPFRSt8ios_baseS4_E[unsigned long fromString(std::basic_string, std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of build/drampower/libdrampower.a(Parameter.os): defined in discarded section `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of build/X86/mem/cache/base.fo (symbol from plugin) `std::basic_string, std::allocator > std::operator
Re: [gem5-users] Integrated DRAMPower model
Hi Andreas, I noticed one issue with the existing energy model. The current model is not modeling the background energy of DDR3 DRAM. If I run a benchmark with 128MB DRAM vs 16GB DRAM, the total energy stays the same. I want to count background energy of DRAM when sitting idle, Please can you tell me, what changes shall I make to the existing code in order to count the background energy of DRAM precisely? The continuous background energy of DRAM is proportional to the size of simulated DRAM and I need to model this. Thanks. Regards, On 10 October 2014 at 15:34, Ahmad Hassan wrote: > > Indeed. That works without any warnings/errors: > > scons --no-lto -j10 build/X86/gem5.fast > > Regards, > > > On 10 October 2014 13:11, Andreas Hansson wrote: > >> Hi Ahmad, >> >> I suspect gcc 4.6 has issues with LTO. I suspect opt works fine, and if >> you want fast, then “--no-lto” should work. >> >> I have a 12.04.03 machine with stock gcc 4.6 and it does have some >> link-time warnings for X86, but no errors. Odd… >> >> Andreas >> >> From: Ahmad Hassan >> Date: Friday, 10 October 2014 10:51 >> To: Andreas Hansson >> Cc: gem5 users mailing list >> >> Subject: Re: [gem5-users] Integrated DRAMPower model >> >> Hi Andreas, >> >> My environment is: >> Ubuntu precise (12.04.3 LTS) >> gcc 4.6 >> >> To be precise, it is a linking error, not the compilation one. >> >> Regards, >> >> >> On 10 October 2014 10:42, Andreas Hansson >> wrote: >> >>> Hi Ahmad, >>> >>> That is odd. Could you elaborate on what environment you are building >>> in? >>> >>> I’ve tested this on Ubuntu 12.04, RHE5/6 and OSX with clang 3.4/3.5, >>> gcc 4.6 and 4.9 without any problems. >>> >>> Andreas >>> >>> From: Ahmad Hassan >>> Date: Friday, 10 October 2014 09:51 >>> To: Andreas Hansson , gem5 users mailing list < >>> gem5-users@gem5.org> >>> Subject: Re: [gem5-users] Integrated DRAMPower model >>> >>> Thanks Andreas. I see compilation error on the trunk tip (changeset: >>> 10433:821cbe4a183b) >>> >>> `std::basic_string, std::allocator > >>> std::operator+, std::allocator >(char >>> const*, std::basic_string, >>> std::allocator > const&)' referenced in section >>> `.text._Z10fromStringIiET_RKSsPFRSt8ios_baseS4_E[int >>> fromString(std::basic_string, >>> std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of >>> build/drampower/libdrampower.a(Parameter.os): defined in discarded section >>> `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of >>> build/X86/mem/cache/base.fo (symbol from plugin) >>> `std::basic_string, std::allocator > >>> std::operator+, std::allocator >(char >>> const*, std::basic_string, >>> std::allocator > const&)' referenced in section >>> `.text._Z10fromStringIjET_RKSsPFRSt8ios_baseS4_E[unsigned int >>> fromString(std::basic_string, >>> std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of >>> build/drampower/libdrampower.a(Parameter.os): defined in discarded section >>> `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of >>> build/X86/mem/cache/base.fo (symbol from plugin) >>> `std::basic_string, std::allocator > >>> std::operator+, std::allocator >(char >>> const*, std::basic_string, >>> std::allocator > const&)' referenced in section >>> `.text._Z10fromStringImET_RKSsPFRSt8ios_baseS4_E[unsigned long >>> fromString(std::basic_string, >>> std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of >>> build/drampower/libdrampower.a(Parameter.os): defined in discarded section >>> `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of >>> build/X86/mem/cache/base.fo (symbol from plugin) >>> `std::basic_string, std::allocator > >>> std::operator+, std::allocator >(char >>> const*, std::basic_string, >>> std::allocator > const&)' referenced in section >>> `.text._Z10fromStringIdET_RKSsPFRSt8ios_baseS4_E[double >>> fromString(std::basic_string, >>> std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of >>> build/drampower/libdrampower.a(Parameter.os): defined in discarded section >>> `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of >>> build/X86/mem/cache/base.fo (symbol from plugin) >>> `std::basic_string, std::allocator > >>> std::operator+, std::allocator >(char >>> const*, std::basic_string, >>> std::allocator > const&)' referenced in section >>> `.text._Z10fromStringIbET_RKSsPFRSt8ios_baseS4_E[bool >>> fromString(std::basic_string, >>> std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of >>> build/drampower/libdrampower.a(Parameter.os): defined in discarded section >>> `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of >>> build/X86/mem/cache/base.fo (symbol from plugin) >>> collect2: ld returned 1 exit status >>> scons: *** [build/X86/gem5.fast.unstripped] Error 1 >>> scons: building terminated because of errors. >>> >>> Regards, >>> >>> >>> On 10 October 2014 09:00, Andreas Hansson via gem5-users < >>> gem5-users@gem5.org> wrot
[gem5-users] parsec vips with M5thread
Compiling VIPS with m5thread gives the following error: /usr/lib/gcc/x86_64-linux-gnu/4.6/../../../x86_64-linux-gnu/libglib-2.0.a(gthread-posix.o): In function `g_cond_impl_new': (.text+0x246): undefined reference to `pthread_condattr_setclock' Is there any workaround to build VIPS using m5thread and run in syscall mode? Thanks Regards, ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] L2 Cache size in fullsystem
Matheus, Booting kernel shows fake cache sizes. If you want to see what cache sizes are configured, then put a print statement in src/mem/cache/base.cc:BaseCache::BaseCache(const Params *p) Regards ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] MMAP a file in SE mode
It turns out that the benchmark was using msync which was not implemented in gem5. As a result, the benchmark was corrupting the gem5 memory. Implemented msync and things seem to work now. Thanks. On 31 October 2014 17:52, Steve Reinhardt wrote: > It should always fault in the same place; the simulator is deterministic. > > Faulting in advancePC() indicates that it's an instruction fetch that's > faulting, which is particularly unusual. > > You should look at an execution trace to see why execution is heading off > into the weeds, if that's what's happening. You can use --debug-start to > turn on the trace just a little bit before the fault, so you don't have to > waste time tracing from the beginning. > > Steve > > On Fri, Oct 31, 2014 at 12:38 PM, Ahmad Hassan > wrote: > >> More interestingly, it always page faults in advancePC method: >> >> #0 0x76416425 in __GI_raise (sig=) at >> ../nptl/sysdeps/unix/sysv/linux/raise.c:64 >> #1 0x76419b8b in __GI_abort () at abort.c:91 >> #2 0x00a37bde in __exit_epilogue(int, char const*, char const*, >> int, char const*) () >> #3 0x008c09a6 in X86ISA::PageFault::invoke(ThreadContext*, >> RefCountingPtr const&) () >> #4 0x0097c8b8 in >> BaseSimpleCPU::advancePC(RefCountingPtr const&) () >> #5 0x00974ed7 in AtomicSimpleCPU::tick() () >> #6 0x00903c91 in EventQueue::serviceOne() () >> #7 0x009211ca in doSimLoop(EventQueue*) () >> #8 0x00921775 in simulate(unsigned long) () >> >> Regards, >> >> >> On 31 October 2014 17:17, Ahmad Hassan wrote: >> >>> Hi Steve, >>> >>> If I just do allocateMem and don't do 'writeBlob', then simulation runs >>> fine without errors but I get '0' values in the result. This is >>> understandable. But If I do writeBlob then I always get page fault >>> exception exactly at the same clock tick (just before the benchmark >>> finishing the execution) >>> >>> Regards, >>> >>> >>> On 31 October 2014 17:11, Steve Reinhardt wrote: >>> >>>> I don't know... that's basically a page fault. Do you know the address >>>> range that your file is mapped to? It may or may not be directly related >>>> to mmap. >>>> >>>> Steve >>>> >>>> On Fri, Oct 31, 2014 at 6:33 AM, Ahmad Hassan >>>> wrote: >>>> >>>>> Hi Steve, >>>>> >>>>> I am running x96 SE mode. The writeBlob() works fine for very small >>>>> test application. For real benchmark with 1GB working set, the simulation >>>>> ends with exception: >>>>> >>>>> panic: Tried to read unmapped address >>>>> 0x280002d773b0. >>>>> 0x2aaab000ULL >>>>> @ tick 771687885000 >>>>> [invoke:build/X86/arch/x86/faults.cc, line 160] >>>>> Memory Usage: 11788528 KBytes >>>>> Program aborted at tick 771687885000 >>>>> >>>>> Any ideas why 0x2800 range is getting problems by writeBlob? >>>>> >>>>> Thanks. >>>>> >>>>> >>>>> >>>>> On 7 October 2014 15:20, Steve Reinhardt wrote: >>>>> >>>>>> We have a patch internally that implements more of mmap(), but >>>>>> unfortunately it's not quite ready to post. >>>>>> >>>>>> If you just want to do a read mapping (you don't care if writes to >>>>>> the mmap'd region get written back to disk), and you don't mind just >>>>>> reading the whole mmap region in up front (which you need to do, since SE >>>>>> mode doesn't support page faulting), it's not too hard; just call >>>>>> p->allocateMem() to allocate the memory in the simulated process, and >>>>>> then >>>>>> read the data out of the file and use writeBlob() to copy it into the >>>>>> memory you just allocated. >>>>>> >>>>>> Steve >>>>>> >>>>>> On Tue, Oct 7, 2014 at 6:14 AM, Ahmad Hassan via gem5-users < >>>>>> gem5-users@gem5.org> wrote: >>>>>> >>>>>>> Hi, >>>>>>> >>>>>>> The existing implementation in GEM5 SE mode only supports MMAP to >>>>>>> /dev/zero. Has anyone implemented MMAP in gem5 that can map a file from >>>>>>> the >>>>>>> disk? If not, how can I extend this? >>>>>>> >>>>>>> Regards, >>>>>>> >>>>>>> ___ >>>>>>> gem5-users mailing list >>>>>>> gem5-users@gem5.org >>>>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>>>>> >>>>>> >>>>>> >>>>> >>>> >>> >> > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] MMAP a file in SE mode
More interestingly, it always page faults in advancePC method: #0 0x76416425 in __GI_raise (sig=) at ../nptl/sysdeps/unix/sysv/linux/raise.c:64 #1 0x76419b8b in __GI_abort () at abort.c:91 #2 0x00a37bde in __exit_epilogue(int, char const*, char const*, int, char const*) () #3 0x008c09a6 in X86ISA::PageFault::invoke(ThreadContext*, RefCountingPtr const&) () #4 0x0097c8b8 in BaseSimpleCPU::advancePC(RefCountingPtr const&) () #5 0x00974ed7 in AtomicSimpleCPU::tick() () #6 0x00903c91 in EventQueue::serviceOne() () #7 0x009211ca in doSimLoop(EventQueue*) () #8 0x00921775 in simulate(unsigned long) () Regards, On 31 October 2014 17:17, Ahmad Hassan wrote: > Hi Steve, > > If I just do allocateMem and don't do 'writeBlob', then simulation runs > fine without errors but I get '0' values in the result. This is > understandable. But If I do writeBlob then I always get page fault > exception exactly at the same clock tick (just before the benchmark > finishing the execution) > > Regards, > > > On 31 October 2014 17:11, Steve Reinhardt wrote: > >> I don't know... that's basically a page fault. Do you know the address >> range that your file is mapped to? It may or may not be directly related >> to mmap. >> >> Steve >> >> On Fri, Oct 31, 2014 at 6:33 AM, Ahmad Hassan >> wrote: >> >>> Hi Steve, >>> >>> I am running x96 SE mode. The writeBlob() works fine for very small test >>> application. For real benchmark with 1GB working set, the simulation ends >>> with exception: >>> >>> panic: Tried to read unmapped address >>> 0x280002d773b0. >>> 0x2aaab000ULL >>> @ tick 771687885000 >>> [invoke:build/X86/arch/x86/faults.cc, line 160] >>> Memory Usage: 11788528 KBytes >>> Program aborted at tick 771687885000 >>> >>> Any ideas why 0x2800 range is getting problems by writeBlob? >>> >>> Thanks. >>> >>> >>> >>> On 7 October 2014 15:20, Steve Reinhardt wrote: >>> >>>> We have a patch internally that implements more of mmap(), but >>>> unfortunately it's not quite ready to post. >>>> >>>> If you just want to do a read mapping (you don't care if writes to the >>>> mmap'd region get written back to disk), and you don't mind just reading >>>> the whole mmap region in up front (which you need to do, since SE mode >>>> doesn't support page faulting), it's not too hard; just call >>>> p->allocateMem() to allocate the memory in the simulated process, and then >>>> read the data out of the file and use writeBlob() to copy it into the >>>> memory you just allocated. >>>> >>>> Steve >>>> >>>> On Tue, Oct 7, 2014 at 6:14 AM, Ahmad Hassan via gem5-users < >>>> gem5-users@gem5.org> wrote: >>>> >>>>> Hi, >>>>> >>>>> The existing implementation in GEM5 SE mode only supports MMAP to >>>>> /dev/zero. Has anyone implemented MMAP in gem5 that can map a file from >>>>> the >>>>> disk? If not, how can I extend this? >>>>> >>>>> Regards, >>>>> >>>>> ___ >>>>> gem5-users mailing list >>>>> gem5-users@gem5.org >>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>>> >>>> >>>> >>> >> > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] MMAP a file in SE mode
Hi Steve, If I just do allocateMem and don't do 'writeBlob', then simulation runs fine without errors but I get '0' values in the result. This is understandable. But If I do writeBlob then I always get page fault exception exactly at the same clock tick (just before the benchmark finishing the execution) Regards, On 31 October 2014 17:11, Steve Reinhardt wrote: > I don't know... that's basically a page fault. Do you know the address > range that your file is mapped to? It may or may not be directly related > to mmap. > > Steve > > On Fri, Oct 31, 2014 at 6:33 AM, Ahmad Hassan > wrote: > >> Hi Steve, >> >> I am running x96 SE mode. The writeBlob() works fine for very small test >> application. For real benchmark with 1GB working set, the simulation ends >> with exception: >> >> panic: Tried to read unmapped address >> 0x280002d773b0. >> 0x2aaab000ULL >> @ tick 771687885000 >> [invoke:build/X86/arch/x86/faults.cc, line 160] >> Memory Usage: 11788528 KBytes >> Program aborted at tick 771687885000 >> >> Any ideas why 0x2800 range is getting problems by writeBlob? >> >> Thanks. >> >> >> >> On 7 October 2014 15:20, Steve Reinhardt wrote: >> >>> We have a patch internally that implements more of mmap(), but >>> unfortunately it's not quite ready to post. >>> >>> If you just want to do a read mapping (you don't care if writes to the >>> mmap'd region get written back to disk), and you don't mind just reading >>> the whole mmap region in up front (which you need to do, since SE mode >>> doesn't support page faulting), it's not too hard; just call >>> p->allocateMem() to allocate the memory in the simulated process, and then >>> read the data out of the file and use writeBlob() to copy it into the >>> memory you just allocated. >>> >>> Steve >>> >>> On Tue, Oct 7, 2014 at 6:14 AM, Ahmad Hassan via gem5-users < >>> gem5-users@gem5.org> wrote: >>> >>>> Hi, >>>> >>>> The existing implementation in GEM5 SE mode only supports MMAP to >>>> /dev/zero. Has anyone implemented MMAP in gem5 that can map a file from the >>>> disk? If not, how can I extend this? >>>> >>>> Regards, >>>> >>>> ___ >>>> gem5-users mailing list >>>> gem5-users@gem5.org >>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>> >>> >>> >> > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] MMAP a file in SE mode
Hi Steve, I am running x96 SE mode. The writeBlob() works fine for very small test application. For real benchmark with 1GB working set, the simulation ends with exception: panic: Tried to read unmapped address 0x280002d773b0. 0x2aaab000ULL @ tick 771687885000 [invoke:build/X86/arch/x86/faults.cc, line 160] Memory Usage: 11788528 KBytes Program aborted at tick 771687885000 Any ideas why 0x2800 range is getting problems by writeBlob? Thanks. On 7 October 2014 15:20, Steve Reinhardt wrote: > We have a patch internally that implements more of mmap(), but > unfortunately it's not quite ready to post. > > If you just want to do a read mapping (you don't care if writes to the > mmap'd region get written back to disk), and you don't mind just reading > the whole mmap region in up front (which you need to do, since SE mode > doesn't support page faulting), it's not too hard; just call > p->allocateMem() to allocate the memory in the simulated process, and then > read the data out of the file and use writeBlob() to copy it into the > memory you just allocated. > > Steve > > On Tue, Oct 7, 2014 at 6:14 AM, Ahmad Hassan via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi, >> >> The existing implementation in GEM5 SE mode only supports MMAP to >> /dev/zero. Has anyone implemented MMAP in gem5 that can map a file from the >> disk? If not, how can I extend this? >> >> Regards, >> >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] System calls query in se mode
Look at: src/arch/x86/linux/syscalls.cc src/sim/syscall_emul.hh Regards, On 31 October 2014 11:25, Debiprasanna Sahoo via gem5-users < gem5-users@gem5.org> wrote: > Hi, > > I am trying to understand the system call "mremapFunc" in se mode. I am > unable to understand how is system call made. I understand that there is no > direct call to this function. Rather it is called using doSyscall using > call parameters and call number, but am unable to track the exact location > of the "mremapFunc" system call. By exact location I mean, where are the > system call name and arguments set. I also tried to search "setSyscallArg" > but again could not figure out how this particular system call is made. > Understanding this call by debugging is also difficult because the call is > made infrequently. I also tried to debug using "gem5.debug" using flag > "SyscallVerbose", but with less luck. Can anyone please help to understand > this or let me know if I want to make this system call after few cycles, > how to do so. > > Thanks, > Debiprasanna Sahoo > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Checkpoint in SE mode
Hi,
I found out that resuming from a checkpoint in SE mode do not preserve the
exact state of the system/application. Example:
fprintf(stderr, "Taking checkpoint...\n");
char buff[500];
chdir("/mnt"); //changing cwd of process
m5_checkpoint(0,0);
fprintf(stderr, "CWD after CP: %s\n", getcwd(buff, 500));
Upon resuming from the above checkpoint, the cwd is reset to gem5 base dir
rather than '/mnt'.
Similarly if we open a file descriptor to a file on disk before a
checkpoint. Then upon resuming, the open file descriptor no longer exists.
Is it the expected behavior?
Regards,
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Integrated DRAMPower model
Indeed. That works without any warnings/errors: scons --no-lto -j10 build/X86/gem5.fast Regards, On 10 October 2014 13:11, Andreas Hansson wrote: > Hi Ahmad, > > I suspect gcc 4.6 has issues with LTO. I suspect opt works fine, and if > you want fast, then “--no-lto” should work. > > I have a 12.04.03 machine with stock gcc 4.6 and it does have some > link-time warnings for X86, but no errors. Odd… > > Andreas > > From: Ahmad Hassan > Date: Friday, 10 October 2014 10:51 > To: Andreas Hansson > Cc: gem5 users mailing list > > Subject: Re: [gem5-users] Integrated DRAMPower model > > Hi Andreas, > > My environment is: > Ubuntu precise (12.04.3 LTS) > gcc 4.6 > > To be precise, it is a linking error, not the compilation one. > > Regards, > > > On 10 October 2014 10:42, Andreas Hansson > wrote: > >> Hi Ahmad, >> >> That is odd. Could you elaborate on what environment you are building >> in? >> >> I’ve tested this on Ubuntu 12.04, RHE5/6 and OSX with clang 3.4/3.5, >> gcc 4.6 and 4.9 without any problems. >> >> Andreas >> >> From: Ahmad Hassan >> Date: Friday, 10 October 2014 09:51 >> To: Andreas Hansson , gem5 users mailing list < >> gem5-users@gem5.org> >> Subject: Re: [gem5-users] Integrated DRAMPower model >> >> Thanks Andreas. I see compilation error on the trunk tip (changeset: >> 10433:821cbe4a183b) >> >> `std::basic_string, std::allocator > >> std::operator+, std::allocator >(char >> const*, std::basic_string, >> std::allocator > const&)' referenced in section >> `.text._Z10fromStringIiET_RKSsPFRSt8ios_baseS4_E[int >> fromString(std::basic_string, >> std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of >> build/drampower/libdrampower.a(Parameter.os): defined in discarded section >> `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of >> build/X86/mem/cache/base.fo (symbol from plugin) >> `std::basic_string, std::allocator > >> std::operator+, std::allocator >(char >> const*, std::basic_string, >> std::allocator > const&)' referenced in section >> `.text._Z10fromStringIjET_RKSsPFRSt8ios_baseS4_E[unsigned int >> fromString(std::basic_string, >> std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of >> build/drampower/libdrampower.a(Parameter.os): defined in discarded section >> `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of >> build/X86/mem/cache/base.fo (symbol from plugin) >> `std::basic_string, std::allocator > >> std::operator+, std::allocator >(char >> const*, std::basic_string, >> std::allocator > const&)' referenced in section >> `.text._Z10fromStringImET_RKSsPFRSt8ios_baseS4_E[unsigned long >> fromString(std::basic_string, >> std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of >> build/drampower/libdrampower.a(Parameter.os): defined in discarded section >> `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of >> build/X86/mem/cache/base.fo (symbol from plugin) >> `std::basic_string, std::allocator > >> std::operator+, std::allocator >(char >> const*, std::basic_string, >> std::allocator > const&)' referenced in section >> `.text._Z10fromStringIdET_RKSsPFRSt8ios_baseS4_E[double >> fromString(std::basic_string, >> std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of >> build/drampower/libdrampower.a(Parameter.os): defined in discarded section >> `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of >> build/X86/mem/cache/base.fo (symbol from plugin) >> `std::basic_string, std::allocator > >> std::operator+, std::allocator >(char >> const*, std::basic_string, >> std::allocator > const&)' referenced in section >> `.text._Z10fromStringIbET_RKSsPFRSt8ios_baseS4_E[bool >> fromString(std::basic_string, >> std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of >> build/drampower/libdrampower.a(Parameter.os): defined in discarded section >> `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of >> build/X86/mem/cache/base.fo (symbol from plugin) >> collect2: ld returned 1 exit status >> scons: *** [build/X86/gem5.fast.unstripped] Error 1 >> scons: building terminated because of errors. >> >> Regards, >> >> >> On 10 October 2014 09:00, Andreas Hansson via gem5-users < >> gem5-users@gem5.org> wrote: >> >>> Hi all, >>> >>> With today’s push to the gem5 trunk (not stable) I am very pleased to >>> announce that DRAMPower is now integrated as the power model backing up the >>> built-in gem5 DRAM controller. Datasheet IDD values are provided for the >>> existing LPDDR2/LPDDR3 and DDR3/DDR4 configurations, but obviously there is >>> nothing stopping people from exploring further. The energy and power >>> results are part of the normal gem5 stats. >>> >>> I would like to especially thank the DRAMPower developers for >>> accommodating the integration, and I am sure there will be a continued >>> mutual benefit from having the two tools work together. With Nilay’s recent >>> Ruby patches this integration should
Re: [gem5-users] Integrated DRAMPower model
Hi Andreas, My environment is: Ubuntu precise (12.04.3 LTS) gcc 4.6 To be precise, it is a linking error, not the compilation one. Regards, On 10 October 2014 10:42, Andreas Hansson wrote: > Hi Ahmad, > > That is odd. Could you elaborate on what environment you are building in? > > I’ve tested this on Ubuntu 12.04, RHE5/6 and OSX with clang 3.4/3.5, gcc > 4.6 and 4.9 without any problems. > > Andreas > > From: Ahmad Hassan > Date: Friday, 10 October 2014 09:51 > To: Andreas Hansson , gem5 users mailing list < > gem5-users@gem5.org> > Subject: Re: [gem5-users] Integrated DRAMPower model > > Thanks Andreas. I see compilation error on the trunk tip (changeset: > 10433:821cbe4a183b) > > `std::basic_string, std::allocator > > std::operator+, std::allocator >(char > const*, std::basic_string, > std::allocator > const&)' referenced in section > `.text._Z10fromStringIiET_RKSsPFRSt8ios_baseS4_E[int > fromString(std::basic_string, > std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of > build/drampower/libdrampower.a(Parameter.os): defined in discarded section > `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of > build/X86/mem/cache/base.fo (symbol from plugin) > `std::basic_string, std::allocator > > std::operator+, std::allocator >(char > const*, std::basic_string, > std::allocator > const&)' referenced in section > `.text._Z10fromStringIjET_RKSsPFRSt8ios_baseS4_E[unsigned int > fromString(std::basic_string, > std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of > build/drampower/libdrampower.a(Parameter.os): defined in discarded section > `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of > build/X86/mem/cache/base.fo (symbol from plugin) > `std::basic_string, std::allocator > > std::operator+, std::allocator >(char > const*, std::basic_string, > std::allocator > const&)' referenced in section > `.text._Z10fromStringImET_RKSsPFRSt8ios_baseS4_E[unsigned long > fromString(std::basic_string, > std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of > build/drampower/libdrampower.a(Parameter.os): defined in discarded section > `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of > build/X86/mem/cache/base.fo (symbol from plugin) > `std::basic_string, std::allocator > > std::operator+, std::allocator >(char > const*, std::basic_string, > std::allocator > const&)' referenced in section > `.text._Z10fromStringIdET_RKSsPFRSt8ios_baseS4_E[double > fromString(std::basic_string, > std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of > build/drampower/libdrampower.a(Parameter.os): defined in discarded section > `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of > build/X86/mem/cache/base.fo (symbol from plugin) > `std::basic_string, std::allocator > > std::operator+, std::allocator >(char > const*, std::basic_string, > std::allocator > const&)' referenced in section > `.text._Z10fromStringIbET_RKSsPFRSt8ios_baseS4_E[bool > fromString(std::basic_string, > std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of > build/drampower/libdrampower.a(Parameter.os): defined in discarded section > `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of > build/X86/mem/cache/base.fo (symbol from plugin) > collect2: ld returned 1 exit status > scons: *** [build/X86/gem5.fast.unstripped] Error 1 > scons: building terminated because of errors. > > Regards, > > > On 10 October 2014 09:00, Andreas Hansson via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi all, >> >> With today’s push to the gem5 trunk (not stable) I am very pleased to >> announce that DRAMPower is now integrated as the power model backing up the >> built-in gem5 DRAM controller. Datasheet IDD values are provided for the >> existing LPDDR2/LPDDR3 and DDR3/DDR4 configurations, but obviously there is >> nothing stopping people from exploring further. The energy and power >> results are part of the normal gem5 stats. >> >> I would like to especially thank the DRAMPower developers for >> accommodating the integration, and I am sure there will be a continued >> mutual benefit from having the two tools work together. With Nilay’s recent >> Ruby patches this integration should also benefit all Ruby users very >> shortly. >> >> We hope all gem5 users enjoy the new functionality. >> >> Kind regards, >> >> Andreas >> >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy the >> information in any medium. Thank you. >> >> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & Wales, Company No: 2557590 >> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & W
Re: [gem5-users] Integrated DRAMPower model
Thanks Andreas. I see compilation error on the trunk tip (changeset: 10433:821cbe4a183b) `std::basic_string, std::allocator > std::operator+, std::allocator >(char const*, std::basic_string, std::allocator > const&)' referenced in section `.text._Z10fromStringIiET_RKSsPFRSt8ios_baseS4_E[int fromString(std::basic_string, std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of build/drampower/libdrampower.a(Parameter.os): defined in discarded section `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of build/X86/mem/cache/base.fo (symbol from plugin) `std::basic_string, std::allocator > std::operator+, std::allocator >(char const*, std::basic_string, std::allocator > const&)' referenced in section `.text._Z10fromStringIjET_RKSsPFRSt8ios_baseS4_E[unsigned int fromString(std::basic_string, std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of build/drampower/libdrampower.a(Parameter.os): defined in discarded section `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of build/X86/mem/cache/base.fo (symbol from plugin) `std::basic_string, std::allocator > std::operator+, std::allocator >(char const*, std::basic_string, std::allocator > const&)' referenced in section `.text._Z10fromStringImET_RKSsPFRSt8ios_baseS4_E[unsigned long fromString(std::basic_string, std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of build/drampower/libdrampower.a(Parameter.os): defined in discarded section `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of build/X86/mem/cache/base.fo (symbol from plugin) `std::basic_string, std::allocator > std::operator+, std::allocator >(char const*, std::basic_string, std::allocator > const&)' referenced in section `.text._Z10fromStringIdET_RKSsPFRSt8ios_baseS4_E[double fromString(std::basic_string, std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of build/drampower/libdrampower.a(Parameter.os): defined in discarded section `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of build/X86/mem/cache/base.fo (symbol from plugin) `std::basic_string, std::allocator > std::operator+, std::allocator >(char const*, std::basic_string, std::allocator > const&)' referenced in section `.text._Z10fromStringIbET_RKSsPFRSt8ios_baseS4_E[bool fromString(std::basic_string, std::allocator > const&, std::ios_base& (*)(std::ios_base&))]' of build/drampower/libdrampower.a(Parameter.os): defined in discarded section `.gnu.linkonce.t._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_' of build/X86/mem/cache/base.fo (symbol from plugin) collect2: ld returned 1 exit status scons: *** [build/X86/gem5.fast.unstripped] Error 1 scons: building terminated because of errors. Regards, On 10 October 2014 09:00, Andreas Hansson via gem5-users < gem5-users@gem5.org> wrote: > Hi all, > > With today’s push to the gem5 trunk (not stable) I am very pleased to > announce that DRAMPower is now integrated as the power model backing up the > built-in gem5 DRAM controller. Datasheet IDD values are provided for the > existing LPDDR2/LPDDR3 and DDR3/DDR4 configurations, but obviously there is > nothing stopping people from exploring further. The energy and power > results are part of the normal gem5 stats. > > I would like to especially thank the DRAMPower developers for > accommodating the integration, and I am sure there will be a continued > mutual benefit from having the two tools work together. With Nilay’s recent > Ruby patches this integration should also benefit all Ruby users very > shortly. > > We hope all gem5 users enjoy the new functionality. > > Kind regards, > > Andreas > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] MMAP a file in SE mode
Hi, The existing implementation in GEM5 SE mode only supports MMAP to /dev/zero. Has anyone implemented MMAP in gem5 that can map a file from the disk? If not, how can I extend this? Regards, ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Configure networking in Gem5 X86 FS
Hi Jiuyue, I have a use case where my benchmark opens a sockets in simulated OS inside gem5 on port 8080. Now I want to send data to this 8080 port from outside gem5 (from host OS). I have done the following: I added a serial port com_2. Now I see that port 3456 is opened for com_1 and 3457 for com_2. Then I send data from host OS to gem5 com_2 using port 3457. The log message shows that gem5 receives this data. Inside gem5 then I bind com_2 to port 8080 using the following commands but com_2 doesn't forward anything to port 8080: mknod /dev/ttyS1 c 4 65 socat /dev/ttyS1,raw,echo=0,crnl tcp4-connect:localhost:8080 << binds successfully Is this approach wrong? Regards, On 27 June 2014 13:27, 马久跃 via gem5-users wrote: > Hi Ahmad, > > 3500 port provided by ethertap is a "virtual ethernet tunnel" (google > TAP/TUN), you can send/recv ethernet packet to/from gem5. > > socat can bind this port to a virtual ethernet device on host os. > > you need to do followings to make this work: > 1) connect Ethernet device to ethertap.tap port using EtherLink, maybe you > have to add "tap" port to py file yourself (see getSlavePort() in > ethertap.cc) > 2) run socat on host os, bind localhost:3500 to tap device (I forgot the > parameter, you may google it), this will create a virtual ethernet device > "tapX" at host os, you can config ip to it as other ethernet device > 3) you also need some modify to send/recv in ethertap cxx source, current > impl send data using a loop which cause checksum failed and packet dropped > at host kernel. I'll post this patch next week. > > Jiuyue > > 在 2014年6月27日，19:02，"Ahmad Hassan" 写道： > > Hi Jiuyue, > > I added ethertap in FSConfig.py as self.ethertap = EtherTap(). I noticed > that it opens the port 3500 on the local host. What does EtherTap do if I > send the data on port 3500? > > Shall I run socat on simulated OS or the host OS? What socket I should > bind to whom, using socat? > > Thanks. > Regards, > > Best Regards, Hassan > > TIP HANA Cloud Computing, Systems Engineering > > *SAP (UK) Limited *| The Concourse, Queen's Rd, Queen's Island, > Titanic Quarter | BT3 9DT Belfast | UK > > > On 26 June 2014 00:07, 马久跃 via gem5-users wrote: > >> Hi Ahmad, >> >> you may try ethertap device + socat tool, they can connect gem5 to host >> machine. but you need some modify to ethertap to make it work with socat. >> >> Jiuyue >> >> 在 2014年6月25日，20:58，"Andreas Hansson via gem5-users" >> 写道： >> >> Hi Ahmad, >> >> There is currently no such functionality in gem5, and networking is >> only supported within one simulator instance. At the moment you can connect >> two systems (as there is no ethernet switch), but on the developer list >> there has been discussions mentioning ongoing work to create an Ethernet >> switch, which would allow more systems (>2) to communicate over Ethernet. >> >> Coming back to your original question, the tricky part with host >> bridging/NATing is the different time scales. The simulated system is >> perhaps 1.000 - 10.000x slower than the host system, and this difference in >> time scale confuses the TCP/IP stack(s). Also, having an external network >> connection will make simulations non-deterministic, which is often >> undesirable. All this said, if you have ideas of how to make it work, >> please feel free to share and discuss on the list. >> >> Andreas >> >> From: Ahmad Hassan via gem5-users >> Reply-To: Ahmad Hassan , gem5 users mailing list >> >> Date: Wednesday, 25 June 2014 04:55 >> To: gem5 users mailing list >> Subject: [gem5-users] Configure networking in Gem5 X86 FS >> >>Hi, >> >> I have set up eth0 interface in X86 FS mode through e1000 driver. But I >> cannot SSH or ping the the host machine or any other IP or the network. I >> noticed that GEM5 does not create any bridge/NAT on the host machine. >> >> How can I configure networking in gem5 so that I can SSH from any >> machine on the network or the host machine into gem5 X86 FS Ubuntu? >> >> Thanks. >> >> -Ahmad >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy the >> information in any medium. Thank you. >> >> ARM Limited, Registered office 110
Re: [gem5-users] Configure networking in Gem5 X86 FS
Hi Jiuyue, I added ethertap in FSConfig.py as self.ethertap = EtherTap(). I noticed that it opens the port 3500 on the local host. What does EtherTap do if I send the data on port 3500? Shall I run socat on simulated OS or the host OS? What socket I should bind to whom, using socat? Thanks. Regards, Best Regards, Hassan TIP HANA Cloud Computing, Systems Engineering *SAP (UK) Limited *| The Concourse, Queen's Rd, Queen's Island, Titanic Quarter | BT3 9DT Belfast | UK On 26 June 2014 00:07, 马久跃 via gem5-users wrote: > Hi Ahmad, > > you may try ethertap device + socat tool, they can connect gem5 to host > machine. but you need some modify to ethertap to make it work with socat. > > Jiuyue > > 在 2014年6月25日，20:58，"Andreas Hansson via gem5-users" > 写道： > > Hi Ahmad, > > There is currently no such functionality in gem5, and networking is only > supported within one simulator instance. At the moment you can connect two > systems (as there is no ethernet switch), but on the developer list there > has been discussions mentioning ongoing work to create an Ethernet switch, > which would allow more systems (>2) to communicate over Ethernet. > > Coming back to your original question, the tricky part with host > bridging/NATing is the different time scales. The simulated system is > perhaps 1.000 - 10.000x slower than the host system, and this difference in > time scale confuses the TCP/IP stack(s). Also, having an external network > connection will make simulations non-deterministic, which is often > undesirable. All this said, if you have ideas of how to make it work, > please feel free to share and discuss on the list. > > Andreas > > From: Ahmad Hassan via gem5-users > Reply-To: Ahmad Hassan , gem5 users mailing list < > gem5-users@gem5.org> > Date: Wednesday, 25 June 2014 04:55 > To: gem5 users mailing list > Subject: [gem5-users] Configure networking in Gem5 X86 FS > >Hi, > > I have set up eth0 interface in X86 FS mode through e1000 driver. But I > cannot SSH or ping the the host machine or any other IP or the network. I > noticed that GEM5 does not create any bridge/NAT on the host machine. > > How can I configure networking in gem5 so that I can SSH from any machine > on the network or the host machine into gem5 X86 FS Ubuntu? > > Thanks. > > -Ahmad > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Configure networking in Gem5 X86 FS
Hi, I have set up eth0 interface in X86 FS mode through e1000 driver. But I cannot SSH or ping the the host machine or any other IP or the network. I noticed that GEM5 does not create any bridge/NAT on the host machine. How can I configure networking in gem5 so that I can SSH from any machine on the network or the host machine into gem5 X86 FS Ubuntu? Thanks. -Ahmad ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] X86 interrupt problem when adding a NIC card
Hi Joonho, Did you manage to configure eth0 in X86 FS? Regards, On 4 February 2014 10:18, 백준호 wrote: > Hello, > > > > I am struggling to add a NIC card to X86 fullsystem. I did the following > thing based on the advice from the previous discussion by Fangfei and David: > >- Add the following line to makeX86System() in FSConfig.py > >self.eth0 = IGbE_e1000(pci_bus = 1, pci_dev = 0, pci_func = 0) > >self.eth0.pio = self.iobus.master > >self.eth0.config = self.iobus.master > >self.eth0.dma = self.iobus.slave > >- Change source_bus_irq in pci_dev_inta MP table entries to match >Interrupt pin number assigned to IGbE_e1000 device. > >source_bus_irq = 0 + (30 << 2) (note: IGbe_e1000 interruptPin = > 0x1e) > > > > But, I get the the following kernel error message "Can't find IRQ for PCI > INT A; probably buggy MP Table" that seems to be observed by other people. > > Do I make some other changes related to interrupt? > > > > Thanks in advance > > > > Sincerely, > > Juno > > > > > > > > > > > > > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Power down state in memory controller
Hi Andreas, Is it possible to run DRAMPower with the current trunk of gem5 please? If yes, then I want to give it a go. Regards, Ahmad On 26 May 2014 14:47, Andreas Hansson via gem5-users wrote: > Hi Amin, > > You are absolutely right. I’m glad to see someone is checking out the > latest commits. > > I’ve got a few follow-up patches that add tXP and tCKE and a basic-level > of low-power mode support. It will probably take a while before we manage > to get these on the review board though, as it also involves integrating > DRAMPower (http://www.es.ele.tue.nl/drampower/) as part of the flow. The > latter is far more convenient compared to manually using the Micron > spreadsheet. > > If you’re keen to work on the power-mode transitions in the DRAM > controller let me know what it is you need (and when). > > Andreas > > From: Amin Farmahini via gem5-users > Reply-To: Amin Farmahini , gem5 users mailing list < > gem5-users@gem5.org> > Date: Sunday, 25 May 2014 17:42 > To: gem5 users mailing list > Subject: [gem5-users] Power down state in memory controller > > Hi, > > It seems like in the current version of gem5, the power down state in the > memory controller is not used. No transition is made to this state (to > either ACT_PDN or PRE_PDN). Am I missing something? > I would guess some changes are needed to support this power state as the > current memory controller doesn't keep track of clock enable. Anyway, this > is a great step towards providing power stats (Thanks to Andreas and his > colleagues). > > Thanks, > Amin > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DDR timing model
Thanks Andreas. This makes a dramatic difference in the results. Regards, On 2 June 2014 15:13, Andreas Hansson wrote: > Hi Ahmad, > > You can tune the page policies of both. By default the DRAMCtrl model in > gem5 uses an open-adaptive policy with FR-FCFS scheduling, which tends to > be the best possible when it comes to row hits. You can change this if you > want, just modify the page_policy parameter of the controller instance. The > default in DRAMSim2 is a simpler open-page policy with a limit of 4 access > to the same page before closing it. Thus, you are far more likely to get > hit by the opening/closing. > > I hope that all makes sense. > > Andreas > > > From: Ahmad Hassan via gem5-users > Reply-To: Ahmad Hassan , gem5 users mailing list < > gem5-users@gem5.org> > Date: Monday, 2 June 2014 15:04 > > To: gem5 users mailing list > Subject: Re: [gem5-users] DDR timing model > > Hi Andreas, > > Thanks for the details. But the same workload gives significant increase > in average memory access time if i run gem5 with integrated dramsim2 and > increase only tRCD and tRP. As you said, both tRCD and tRP are associated > with opening and closing of row. The results of dramsim2 and gem5 DDR3 > memory model suggests that gem5 keeps the rows open for much longer > duration which causes significantly higher pageHitRate. > > Regards, > > On 2 June 2014 10:36, Andreas Hansson wrote: > >> Hi Ahmad, >> >> Increasing tRCD and tRP will essentially make it more costly to open >> and close a page. If you have good page hit-rate, and good distribution >> over the banks, then the effects of the increased timings can be hidden (at >> least from the perspective of the average latency). When you increase tCL >> you are delaying every single access. >> >> bytesPerActivate is a histogram statistic associated with the DRAM >> controller. You should find it in the stats.txt along with all the other >> stats. >> >> Andreas >> >> From: Ahmad Hassan via gem5-users >> Reply-To: Ahmad Hassan , gem5 users mailing list >> >> Date: Monday, 2 June 2014 10:29 >> To: gem5 users mailing list >> Subject: [gem5-users] DDR timing model >> >>Hi Andreas, >> >> [Moving discussion from http://reviews.gem5.org/r/2109] >> >> If I only increase the tCL parameter from 13.75ns to 61ns [4.4x times >> default DDR3), then I notice 3.2x times increase in avgMemAccLat. This is >> what we should expect. Can we use tCL to simulate slow DDR3? My >> understanding is that, we cannot do that because tCL represents column >> address strobe and it affects bandwidth. >> >> But I cannot produce the same result by changing tRCD = '61ns', tRP = >> '165ns'. tRCD affects read latency and tRP affects write latency. I only >> get an increase in avgMemAccLat by 1.2x times default DDR3. >> >> Results: >> >> For default DDR3: >> avgMemAccLat22133.24 >> totMemAccLat 12166996811 >> >> For tRCD = '61ns', tRP = '165ns'. >> avgMemAccLat27473.08 >> totMemAccLat 15104591550 >> >> For tCL = '61ns' >> avgMemAccLat71630.94 >> totMemAccLat 39376746052 >> >> I did not find any 'bytesPerActive' attribute in stats file. Where shall >> I see this? >> >> Thanks. >> >> >> >> >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy the >> information in any medium. Thank you. >> >> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & Wales, Company No: 2557590 >> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & Wales, Company No: 2548782 >> > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DDR timing model
Hi Andreas, Thanks for the details. But the same workload gives significant increase in average memory access time if i run gem5 with integrated dramsim2 and increase only tRCD and tRP. As you said, both tRCD and tRP are associated with opening and closing of row. The results of dramsim2 and gem5 DDR3 memory model suggests that gem5 keeps the rows open for much longer duration which causes significantly higher pageHitRate. Regards, On 2 June 2014 10:36, Andreas Hansson wrote: > Hi Ahmad, > > Increasing tRCD and tRP will essentially make it more costly to open and > close a page. If you have good page hit-rate, and good distribution over > the banks, then the effects of the increased timings can be hidden (at > least from the perspective of the average latency). When you increase tCL > you are delaying every single access. > > bytesPerActivate is a histogram statistic associated with the DRAM > controller. You should find it in the stats.txt along with all the other > stats. > > Andreas > > From: Ahmad Hassan via gem5-users > Reply-To: Ahmad Hassan , gem5 users mailing list < > gem5-users@gem5.org> > Date: Monday, 2 June 2014 10:29 > To: gem5 users mailing list > Subject: [gem5-users] DDR timing model > >Hi Andreas, > > [Moving discussion from http://reviews.gem5.org/r/2109] > > If I only increase the tCL parameter from 13.75ns to 61ns [4.4x times > default DDR3), then I notice 3.2x times increase in avgMemAccLat. This is > what we should expect. Can we use tCL to simulate slow DDR3? My > understanding is that, we cannot do that because tCL represents column > address strobe and it affects bandwidth. > > But I cannot produce the same result by changing tRCD = '61ns', tRP = > '165ns'. tRCD affects read latency and tRP affects write latency. I only > get an increase in avgMemAccLat by 1.2x times default DDR3. > > Results: > > For default DDR3: > avgMemAccLat22133.24 > totMemAccLat 12166996811 > > For tRCD = '61ns', tRP = '165ns'. > avgMemAccLat27473.08 > totMemAccLat 15104591550 > > For tCL = '61ns' > avgMemAccLat71630.94 > totMemAccLat 39376746052 > > I did not find any 'bytesPerActive' attribute in stats file. Where shall > I see this? > > Thanks. > > > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] DDR timing model
Hi Andreas, [Moving discussion from http://reviews.gem5.org/r/2109] If I only increase the tCL parameter from 13.75ns to 61ns [4.4x times default DDR3), then I notice 3.2x times increase in avgMemAccLat. This is what we should expect. Can we use tCL to simulate slow DDR3? My understanding is that, we cannot do that because tCL represents column address strobe and it affects bandwidth. But I cannot produce the same result by changing tRCD = '61ns', tRP = '165ns'. tRCD affects read latency and tRP affects write latency. I only get an increase in avgMemAccLat by 1.2x times default DDR3. Results: For default DDR3: avgMemAccLat22133.24 totMemAccLat 12166996811 For tRCD = '61ns', tRP = '165ns'. avgMemAccLat27473.08 totMemAccLat 15104591550 For tCL = '61ns' avgMemAccLat71630.94 totMemAccLat 39376746052 I did not find any 'bytesPerActive' attribute in stats file. Where shall I see this? Thanks. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] GEM5 maximum disk size limit
Hi, gem5img.py utility in gem5 only allows creating disk images up to 7.8GB (8455200768). Is it possible to create larger disk image around 200GB for GEM5? Does GEM5 support that? If not, then what are the other alternatives to use larger data set (200GB) for a benchmark running in gem5 FS mode. Thanks. Best Regards, Hassan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
