[gem5-users] Cacheline status throughout hierarchy

2022-04-11 Thread Alex Freij via gem5-users
Hi all,

I'm looking for a way to count the total number of dirty/clean blocks
within the cache hierarchy to get an overall ratio from each cache
simulated. So far I haven't had much luck in finding a straightforward way
to do this other than running through the cache/base.cc file and manually
looking for when a write or evict is issued. Any help would be appreciated!

Sincerely,

- Alex
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[gem5-users] Re: How to modify the gem5 simulator code?

2020-11-19 Thread Alex Freij via gem5-users
Hi,

The files you want to look at for the memory access are src/mem/
dram_ctrl.cc/.hh and src/mem/DRAMCtrl.py for issuing requests from the
memory controller. The memory access itself is performed in
DRAMCtrl::accessAndRespond, with a call to access() which is defined in
src/mem/abstract_mem.cc.

 This may have changed with recent gem5 updates but I don't think there is
a field to identify the requesting core so you can differentiate between
them, but perhaps adding a field in the packet class definition and
assigning the threadID would help you do that.

Sincerely,

- Alex
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[gem5-users] Benchmark terminating early

2020-07-10 Thread Alex Freij via gem5-users
Hello all,

I'm running a single core X86 o3 sim with SPEC2006 benchmarks, and have run
into a scenario where some of the benchmarks are terminating early. Using
the "DRAM" debug flag, I see this message upon termination:

Exiting @ tick 67067500 because exiting with last active thread context
67067500: system.mem_ctrls_0: Computing stats due to a dump callback
67067500: system.mem_ctrls_1: Computing stats due to a dump callback

Does anyone know of any way to properly debug the root cause of this issue?
I have also used the Exec and ExecAll flags, but not much more information
was provided.

Thank you,

- Alex
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[gem5-users] Re: Adding new source files

2020-05-07 Thread Alex Freij via gem5-users
Hi Francisco,

Thanks for the quick reply! Yes I did; the .cc/.hh files are present and
are in the same directory. I've also realized something else: the file I'm
creating should reside in X86/mem/ (since that's where the .cc/.hh files
reside and the SConscript in that directory was updated), while SCons is
failing and stating that the file can't be found in the X86/sim directory.

- Alex

On Thu, May 7, 2020 at 11:04 AM Francisco Carlos via gem5-users <
gem5-users@gem5.org> wrote:

> Did you create myFile.cc? myFile.cc should be in the same directory of the
> Sconscript that you added because you used the path 'myFile.cc' to the file.
>
> I hope this helps.
>
>
> --
> Francisco Carlos Silva Junior
> Phd Student
>
> --
> *De:* Alex Freij via gem5-users 
> *Enviado:* quinta-feira, 7 de maio de 2020 11:31
> *Para:* gem5-users@gem5.org 
> *Cc:* Alex Freij 
> *Assunto:* [gem5-users] Adding new source files
>
> Hi all,
>
> I'm trying to understand how to add source files to the gem5 project
> without the need to create a SimObject. I've added `Source('myFile.cc')`
> into the respective SConscript file, but when I try to build I get this
> message:
>
> scons: *** [build/X86/sim/myFile.o] Source `build/X86/sim/myFile.cc' not 
> found, needed by target `build/X86/sim/myFile.o'.
> scons: building terminated because of errors.
>
> This is a very rookie question, but guidance would be appreciated!
>
> - Alex
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[gem5-users] Adding new source files

2020-05-07 Thread Alex Freij via gem5-users
Hi all,

I'm trying to understand how to add source files to the gem5 project
without the need to create a SimObject. I've added `Source('myFile.cc')`
into the respective SConscript file, but when I try to build I get this
message:

scons: *** [build/X86/sim/myFile.o] Source `build/X86/sim/myFile.cc'
not found, needed by target `build/X86/sim/myFile.o'.
scons: building terminated because of errors.

This is a very rookie question, but guidance would be appreciated!

- Alex
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