Hello Users, I have defined a memory type for Normal Memory allocation using NMRR register. This memory type has the Inner Cacheable property, "Non-Cacheable" and Outer Cacheable property, "WriteBack-WriteAllocate". The memory access to the memory region allocated using this memory type is by-passing both L1 cache and L2 Cache. This means both L1 and L2 falls in the Inner Cacheable domain. According ARM Architecture Reference Manual, It is possible to have One inner cache(L1) and One outer Cache(L2), which is implementation defined.
If my understanding is correct, in real systems, Cache that is connected as the slave to the AMBA Bus, falls under Outer Cacheable domain. How this can be controlled in Gem5? Thanks, Prathap
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