Re: [gem5-users] Set number of ports to dcache and l2 cache in gem5
Thank you so much Jason, your reply was very much required. On Thu, Dec 13, 2018 at 1:17 PM Jason Lowe-Power wrote: > Hi Abhishek, > > I wouldn't trust the parameters you mentioned to correctly model cache > ports as you want. The bandwidth between the core and the caches is not > flexibly modeled with the classic caches or with Ruby right now. I believe > there are some patches on the code review site that try to make this better > (they relate to the ARM vector extension patch series). For the bandwidth > between caches, I think it's even worse. You can configure the interconnect > (e.g., crossbar) to have a particular bandwidth which is modeled in detail > for the classic cache, but the cache itself doesn't model bandwidth well. > For Ruby, you can use the BankedCache models if your coherence protocol > correctly requests those resources, but most of the protocols don't > implement that. Also, the BankedCache model is a quick and dirty model for > cache bandwidth, not a detailed port model. > > As far as "I have seen this multi-port configuration in most gem5 papers", > I would guess that one person wrote it once and then everyone else copied > it. I doubt that there was significant care given to the cache bandwidth > model in all but a few papers (if that). > > Hope this helps, > Jason > > On Tue, Dec 11, 2018 at 10:51 PM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >> Hello Everyone, >> >> I want to simulate multi-port cache configuration for O3CPU, for example, >> >> Private L1: Split I/D, 64KB, 4-way, 64B blocks, *3ports,* 1ns, 32MSHRs, >> LRU >> Private L2: 256kB, 8-way, *2 ports,* 3ns, 32MSHRs, LRU >> >> How should I set highlighted ports in gem5 i.e. *3 ports* for L1 and *2 >> ports* for L2? >> >> I know there is a parameter in O3CPU.py which is *cacheStorePorts, *which >> is for stores which will limit store port to L1-dcache, and where is Load >> FU, I searched in *FuncUnitConfig.py *but there was no LoadFU, is* class >> ReadPort* mean LoadFu? >> >> And then how to set the number of ports for L2? >> >> I have seen this multi-port configuration in most gem5 papers, so if >> anyone knows how to do it please let me know! >> >> I have seen this post: >> https://www.mail-archive.com/gem5-users@gem5.org/msg12912.html >> But still, it does not say how to set this parameter for L1 and L2 and >> where is LoadFU. >> >> >> Best regards, >> >> Abhishek >> > ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Set number of ports to dcache and l2 cache in gem5
Hi Abhishek, I wouldn't trust the parameters you mentioned to correctly model cache ports as you want. The bandwidth between the core and the caches is not flexibly modeled with the classic caches or with Ruby right now. I believe there are some patches on the code review site that try to make this better (they relate to the ARM vector extension patch series). For the bandwidth between caches, I think it's even worse. You can configure the interconnect (e.g., crossbar) to have a particular bandwidth which is modeled in detail for the classic cache, but the cache itself doesn't model bandwidth well. For Ruby, you can use the BankedCache models if your coherence protocol correctly requests those resources, but most of the protocols don't implement that. Also, the BankedCache model is a quick and dirty model for cache bandwidth, not a detailed port model. As far as "I have seen this multi-port configuration in most gem5 papers", I would guess that one person wrote it once and then everyone else copied it. I doubt that there was significant care given to the cache bandwidth model in all but a few papers (if that). Hope this helps, Jason On Tue, Dec 11, 2018 at 10:51 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hello Everyone, > > I want to simulate multi-port cache configuration for O3CPU, for example, > > Private L1: Split I/D, 64KB, 4-way, 64B blocks, *3ports,* 1ns, 32MSHRs, > LRU > Private L2: 256kB, 8-way, *2 ports,* 3ns, 32MSHRs, LRU > > How should I set highlighted ports in gem5 i.e. *3 ports* for L1 and *2 > ports* for L2? > > I know there is a parameter in O3CPU.py which is *cacheStorePorts, *which > is for stores which will limit store port to L1-dcache, and where is Load > FU, I searched in *FuncUnitConfig.py *but there was no LoadFU, is* class > ReadPort* mean LoadFu? > > And then how to set the number of ports for L2? > > I have seen this multi-port configuration in most gem5 papers, so if > anyone knows how to do it please let me know! > > I have seen this post: > https://www.mail-archive.com/gem5-users@gem5.org/msg12912.html > But still, it does not say how to set this parameter for L1 and L2 and > where is LoadFU. > > > Best regards, > > Abhishek > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Set number of ports to dcache and l2 cache in gem5
Hello Everyone, I want to simulate multi-port cache configuration for O3CPU, for example, Private L1: Split I/D, 64KB, 4-way, 64B blocks, *3ports,* 1ns, 32MSHRs, LRU Private L2: 256kB, 8-way, *2 ports,* 3ns, 32MSHRs, LRU How should I set highlighted ports in gem5 i.e. *3 ports* for L1 and *2 ports* for L2? I know there is a parameter in O3CPU.py which is *cacheStorePorts, *which is for stores which will limit store port to L1-dcache, and where is Load FU, I searched in *FuncUnitConfig.py *but there was no LoadFU, is* class ReadPort* mean LoadFu? And then how to set the number of ports for L2? I have seen this multi-port configuration in most gem5 papers, so if anyone knows how to do it please let me know! I have seen this post: https://www.mail-archive.com/gem5-users@gem5.org/msg12912.html But still, it does not say how to set this parameter for L1 and L2 and where is LoadFU. Best regards, Abhishek ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
