Hi Prathap,
That’s unfortunate. Perhaps you can add some debug printouts to figure out what
is going wrong in the restoring.
In either case, I would suggest to use the SimpleMemory for getting to the
region of interest (as it is much faster).
Also, you are probably better off with the native gem5 DRAMCtrl model as it is
much faster, and far more tested.
Andreas
From: Prathap Kolakkampadath via gem5-users
gem5-users@gem5.orgmailto:gem5-users@gem5.org
Reply-To: Prathap Kolakkampadath
kvprat...@gmail.commailto:kvprat...@gmail.com, gem5 users mailing list
gem5-users@gem5.orgmailto:gem5-users@gem5.org
Date: Tuesday, 9 September 2014 18:32
To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org
Subject: [gem5-users] Switching CPU type from a checkpoint fails when using
memory type dramsim2
Hello Everybody,
I have created a checkpoint with cpu type 'atomic' and mem type 'dramsim2.
While switching to cpu type 'detailed' from this checkpoint simulation fails
with below error.
Switch at curTick count:1
info: Entering event queue @ 3534903961500. Starting simulation...
writing vis file to
ext/dramsim2/DRAMSim2//results//DDR3_micron_32M_8B_x8_sg15/2GB.1Ch.1R.scheme2.open_page.32TQ.32CQ.RtB.pRank.vis
Switched CPUS @ tick 3534903971500
switching cpus
REAL SIMULATION
info: Entering event queue @ 3534903971500. Starting simulation...
gem5.opt: build/ARM/mem/dramsim2.cc:293: void DRAMSim2::readComplete(unsigned
int, uint64_t, uint64_t): Assertion `cycle == divCeil(curTick() - startTick,
wrapper.clockPeriod() * SimClock::Int::ns)' failed.
Program aborted at tick 3535124958500
Aborted (core dumped)
Do anyone know what went wrong?
Thanks,
Prathap
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